The 'ALS191A are synchronous 4-bit reversible up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters.
The outputs of the four flip-flops are triggered on a
low-to-high-level transition of the clock (CLK) input if the count
enable (
) input is low.
A high at inhibits
counting. The direction of the count is determined by the level of
the down/up (D/U\) input. When D/U\ is low, the counter counts up,
and when D/U\ is high, the counter counts down.
These counters feature a fully independent clock circuit. Changes
at the control inputs ( and
D/U\) that modify the operating mode have no effect on the contents
of the counter until clocking occurs. The function of the counter is
dictated solely by the conditions meeting the stable setup and hold
times.
These counters are fully programmable. Each output can be preset
to either level by placing a low on the 
input and entering the desired data at the data inputs.
The output changes to agree with the data inputs independently of the
level of the clock input. This feature allows the counters to be used
as modulo-N dividers by simply modifying the count length with the
preset inputs.
CLK, D/U\, and are buffered
to lower the drive requirement, which significantly reduces the
loading on (current required by) clock drivers, for long parallel
words.
Two outputs are available to perform the cascading function:
ripple clock and maximum/minimum count. The latter output produces a
high-level output pulse with a duration approximately equal to one
complete cycle of the clock while the count is minimum (0) counting
down or maximum (15) counting up. The ripple-clock output (
) produces a low-level output pulse
under those same conditions, but only while the clock input is low.
The counter easily can be cascaded by feeding the ripple-clock output
to the enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. The
maximum/minimum count (MAX/MIN) output can be used to accomplish look
ahead for high-speed operation.
The SN54ALS191A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS191A is characterized for operation from 0°C to 70°C.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | Synchronous 4-Bit Up/Down Binary Counters datasheet (Rev. C) | 01 Jul 1996 | |
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dec 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 Aug 2002 | ||
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 01 Aug 1997 | ||
| Application note | Designing With Logic (Rev. C) | 01 Jun 1997 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 01 Oct 1996 | ||
| Application note | Live Insertion | 01 Oct 1996 | ||
| Application note | Advanced Schottky (ALS and AS) Logic Families | 01 Aug 1995 |
For additional terms or required resources, click any title below to view the detail page where available.
The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,
| Package | Pins | Download |
|---|---|---|
| PDIP (N) | 16 | View options |
| SOIC (D) | 16 | View options |
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