SN74ALVC125 Quadruple Bus Buffer Gates With 3-State Outputs | TI.com

SN74ALVC125
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Quadruple Bus Buffer Gates With 3-State Outputs

Quadruple Bus Buffer Gates With 3-State Outputs - SN74ALVC125
Datasheet
 

Description

This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVC125 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Features

  • Operates From 1.65 V to 3.6 V
  • Max tpd of 2.8 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Parametrics

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Part number Order Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) IOL (Max) (mA) IOH (Max) (mA) ICC (uA) Input type Output type Features Data rate (Mbps) Rating Package Group
SN74ALVC125 Order now ALVC     1.65     3.6     4     24     -24     10     Standard CMOS     3-State     Balanced outputs
Very high speed (tpd 5-10ns)
Over-voltage tolerant inputs    
200     Catalog     SOIC | 14
SO | 14
TSSOP | 14
TVSOP | 14