SN74AS175B Quadruple D-Type Positive-Edge-Triggered Flip-Flops With Clear | TI.com

SN74AS175B
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Quadruple D-Type Positive-Edge-Triggered Flip-Flops With Clear

Quadruple D-Type Positive-Edge-Triggered Flip-Flops With Clear - SN74AS175B
Datasheet
 

Description

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.

Features

  • ’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs
  • ’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail Outputs
  • Buffered Clock and Direct-Clear Inputs
  • Applications Include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators
  • Fully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)

Parametrics

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Part number Order Technology Family Input type Output type VCC (Min) (V) VCC (Max) (V) Channels (#) Clock Frequency (Max) (MHz) ICC (uA) IOL (Max) (mA) IOH (Max) (mA) Features Rating Package Group
SN74AS175B Order now AS     Bipolar     Push-Pull     4.5     5.5     4     100     34000     20     -2     Very high speed (tpd 5-10ns)     Catalog     PDIP | 16
SOIC | 16
SO | 16    
SN54AS175B Samples not available AS     Bipolar     Push-Pull     4.5     5.5     4     100     34000     20     -2     Very high speed (tpd 5-10ns)     Military     CDIP | 16