SN74AVCH16T245 16-Bit Dual Supply Bus Transceiver with Configurable Voltage Translation and 3-State Outputs | TI.com

SN74AVCH16T245 (ACTIVE)

16-Bit Dual Supply Bus Transceiver with Configurable Voltage Translation and 3-State Outputs

 

Description

This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVCH16T245 device is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. The device is operational with VCCA/VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCH16T245 control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA.

The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This device is fully specified for partial-power-down applications using Ioff.

The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74AVCH16T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated.

Features

  • VCC Isolation Feature – If Either VCC Input is at GND, Both Ports are in the High-Impedance State
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • Overvoltage-Tolerant Inputs and Outputs Allow Mixed Voltage-Mode Data Communications
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2 V to 3.6 V Power-Supply Range
  • Ioff Supports Partial-Power-Down Mode Operation
  • I/Os are 4.6 V Tolerant
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup and Pulldown Resistors
  • Maximum Data Rates
    • 380 Mbps (1.8 V to 3.3 V Level-Shifting)
    • 200 Mbps (<1.8 V to 3.3 V Level-Shifting)
    • 200 Mbps (Level-Shifting to 2.5 V or 1.8 V)
    • 150 Mbps (Level-Shifting to 1.5 V)
    • 100 Mbps (Level-Shifting to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 8000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Parametrics

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Part number Order Technology Family Application Bits (#) High input voltage (Min) (Vih) High input voltage (Max) (Vih) Output voltage (Min) (V) Output voltage (Max) (V) IOH (Max) (mA) IOL (Max) (mA) Package Group Rating
SN74AVCH16T245 Order now AVC       16     1     3.6     1.2     3.6     -12     12     BGA MICROSTAR JUNIOR | 56
TSSOP | 48
TVSOP | 48    
Catalog    
SN74AVC16T245 Order now AVC     RGMII     16     0.78     3.6     1.2     3.6     -12     12     BGA MICROSTAR JUNIOR | 56
TSSOP | 48
TVSOP | 48    
Catalog    
SN74AVC16T245-Q1 Order now AVC     RGMII     16     0.78     3.6     1.2     3.6     -12     12     TVSOP | 48     Automotive    
SN74AVCH1T45 Order now AVC     GPIO     1     1     3.6     1.2     3.6     -12     12     DSBGA | 6
SC70 | 6
SOT-23 | 6    
Catalog    
SN74AVCH20T245 Order now AVC       20     0.8     3.6     1.2     3.6     -12     12     BGA MICROSTAR JUNIOR | 56
TSSOP | 56
TVSOP | 56    
Catalog    
SN74AVCH2T45 Order now AVC     GPIO
I2S    
2     0.8     3.6     1.2     3.6     -12     12     DSBGA | 8
SM8 | 8
VSSOP | 8    
Catalog    
SN74AVCH4T245 Order now AVC     UART
JTAG
SPI    
4     1.2