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SN74HC02-EP

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Enhanced product 4-ch, 2-input, 2-V to 6-V NOR gate

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Data sheet

SN74HC02-EP

ACTIVE
Data sheet Order now

Product details

Technology family HC Number of channels 4 Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Inputs per channel 2 IOL (max) (mA) 4 IOH (max) (mA) -4 Output type Push-Pull Input type Standard CMOS Features High speed (tpd 10- 50ns) Data rate (max) (Mbps) 28 Rating HiRel Enhanced Product Operating temperature range (°C) -40 to 125
Technology family HC Number of channels 4 Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Inputs per channel 2 IOL (max) (mA) 4 IOH (max) (mA) -4 Output type Push-Pull Input type Standard CMOS Features High speed (tpd 10- 50ns) Data rate (max) (Mbps) 28 Rating HiRel Enhanced Product Operating temperature range (°C) -40 to 125
TSSOP (PW) 14 32 mm² 5 x 6.4
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of Up To –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • 2-V to 6-V VCC Operation
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 20-µA Max ICC
  • Typical tpd = 8 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of Up To –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • 2-V to 6-V VCC Operation
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 20-µA Max ICC
  • Typical tpd = 8 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

The SN74HC02 contains four independent 2-input NOR gates. It performs the Boolean function Y = (A + B)\ or Y = A\ • B\ in positive logic.

The SN74HC02 contains four independent 2-input NOR gates. It performs the Boolean function Y = (A + B)\ or Y = A\ • B\ in positive logic.
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Technical documentation

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Type Title Date
* Data sheet SN74HC02-EP datasheet (Rev. A) 06 Jan 2004
* VID SN74HC02-EP VID V6204687 21 Jun 2016
* Radiation & reliability report SN74HC02QPWREP Reliability Report 05 Sep 2013
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

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TSSOP (PW) 14 View options
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