SN74HC109 Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset | TI.com

SN74HC109 (ACTIVE)

Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset

Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset - SN74HC109
Datasheet
 

Description

These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.

Features

  • Wide Operating Voltage Range of 2 V to 6 V
  • Low Input Current of 1 µA Max
  • High-Current Outputs Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 40-µA Max ICC
  • Typical tpd = 12 ns
  • ±4-mA Output Drive at 5 V

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Parametrics Compare all products in J-K flip-flop

 
Technology Family
VCC (Min) (V)
VCC (Max) (V)
Bits (#)
Voltage (Nom) (V)
F @ nom voltage (Max) (Mhz)
ICC @ nom voltage (Max) (mA)
tpd @ Nom Voltage (Max) (ns)
IOL (Max) (mA)
IOH (Max) (mA)
Rating
SN74HC109 SN54HC109
HC     HC    
2     2    
6     6    
2     2    
3.3
5    
3.3
5    
70     70    
0.04     0.04    
58     58    
4     -4    
-4     4    
Catalog     Military