These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.
These flip-flops are guaranteed to respond to clock frequencies ranging form 0 to 30 megahertz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 39 milliwatts per flip-flop for the ´273 and 10 milliwatts for the ´LS273.
|Part number||Order||Technology Family||Input type||Output type||VCC (Min) (V)||VCC (Max) (V)||Channels (#)||Clock Frequency (Max) (MHz)||ICC (uA)||IOL (Max) (mA)||IOH (Max) (mA)||Features||Rating||Package Group|
||LS||Bipolar||Push-Pull||4.75||5.25||8||35||27000||8||-0.4||High speed (tpd 10-50ns)||Catalog||
PDIP | 20
SOIC | 20
SO | 20
|SN54LS273||Samples not available||LS||Bipolar||Push-Pull||4.5||5.5||8||35||27000||8||-0.4||High speed (tpd 10-50ns)||Military||
CDIP | 20
CFP | 20
LCCC | 20