SN74LV138AT 3-Line To 8-Line Decoder/Demultiplexers | TI.com

SN74LV138AT
This product has been released to the market and is available for purchase. For some products, newer alternatives may be available.
3-Line To 8-Line Decoder/Demultiplexers

3-Line To 8-Line Decoder/Demultiplexers - SN74LV138AT
Datasheet
 

Description

The SN74LV138AT is a 3-line to 8-line decoder/demultiplexer, designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of the decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions at the binary-select inputs (A, B, C) and the three enable inputs (G1, G2A, G2B) select one of eight output lines. The two active-low (G2A, G2B) and one active-high (G1) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

This device is fully specified for partial-power-down application susing Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Features

  • Inputs Are TTL-Voltage Compatible
  • 4.5-V to 5.5-V VCC Operation
  • Max tpd of 7.6 ns at 5 V
  • Typical VOLP (Output Ground Bounce)<0.8 V at VCC = 5 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)>>2.3 V at VCC = 5 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Parametrics

Compare all products in Encoders & decoders Email Download to Excel
Part number Order Function Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) Voltage (Nom) (V) F @ nom voltage (Max) (MHz) ICC @ nom voltage (Max) (mA) tpd @ nom Voltage (Max) (ns) Configuration Type IOL (Max) (mA) IOH (Max) (mA) Rating Operating temperature range (C) Package Group Package size: mm2:W x L (PKG) Bits (#) Digital input leakage (Max) (uA) ESD CDM (kV) ESD HBM (kV)
SN74LV138AT Order now Decoder
Demultiplexer    
LV-AT     4.5     5.5     1     3.3     70     0.02     13     3:8     Standard     12     -12     Catalog     -40 to 125     SOIC | 16
SSOP | 16
TSSOP | 16
TVSOP | 16
VQFN | 16    
16SOIC: 59 mm2: 6 x 9.9 (SOIC | 16)
16SSOP: 48 mm2: 7.8 x 6.2 (SSOP | 16)
16TSSOP: 22 mm2: 4.4 x 5 (TSSOP | 16)
16TVSOP: 23 mm2: 6.4 x 3.6 (TVSOP | 16)
16VQFN: 14 mm2: 3.5 x 4 (VQFN | 16)    
8     5     0.75     2