SN74LVC1G79 Single Positive-Edge-Triggered D-Type Flip-Flop | TI.com

SN74LVC1G79
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Single Positive-Edge-Triggered D-Type Flip-Flop

 

Description

The SN74LVC1G79 device is a single positive-edge-triggered D-type flip-flop that is designed for 1.65-V to 5.5-V VCC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

Features

  • Available in the Texas Instruments
    NanoFree™ Package
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Supports Down Translation to VCC
  • Max tpd of 6 ns at 3.3 V and 50 pF load
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff supports Partial-Power-Down Mode and Back-Drive Protection

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Parametrics

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Part number Order Technology Family Input type Output type VCC (Min) (V) VCC (Max) (V) Channels (#) Clock Frequency (Max) (MHz) ICC (uA) IOL (Max) (mA) IOH (Max) (mA) Features Rating Package Group
SN74LVC1G79 Order now LVC     Standard CMOS     Push-Pull     1.65     5.5     1     150     10     32     -32     Balanced outputs     Catalog     DSBGA | 5
SC70 | 5
SOT-23 | 5
SOT-5X3 | 5    
SN74AUC1G79 Samples not available AUC     Standard CMOS     Push-Pull     0.8     2.7     1     275     10     9     -9     Balanced outputs
Ultra high speed (tpd <5ns)
Over-voltage tolerant inputs
Partial power down (Ioff)    
Catalog     SC70 | 5
SOT-23 | 5    
SN74AUP1G74 Order now AUP     Standard CMOS     Push-Pull     0.8     3.6     1     160     0.9     4     -4     Balanced outputs
Very high speed (tpd 5-10ns)
Over-voltage tolerant inputs
Partial power down (Ioff)    
Catalog     DSBGA | 8
DSBGA | 8
UQFN | 8
VSSOP | 8
X2SON | 8    
SN74AUP1G79 Order now AUP     Standard CMOS     Push-Pull     0.8     3.6     1     260     0.9     4     -4     Balanced outputs
Very high speed (tpd 5-10ns)
Over-voltage tolerant inputs
Partial power down (Ioff)    
Catalog     DSBGA | 5
DSBGA | 6
SC70 | 5
SON | 6
SON | 6
SOT-23 | 5
SOT-5X3 | 5
X2SON | 5    
SN74AUP1G80 Order now AUP     Standard CMOS     Push-Pull     0.8     3.6     1     260     0.9     4     -4     Balanced outputs
Very high speed (tpd 5-10ns)
Over-voltage tolerant inputs
Partial power down (Ioff)    
Catalog     DSBGA | 5
DSBGA | 6
SC70 | 5
SON | 6
SON | 6
SOT-23 | 5
X2SON | 5    
SN74AUP2G79 Order now AUP     Standard CMOS     Push-Pull     0.8     3.6     2     260     0.9     4