This automotive AEC-Q100 qualified single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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|VCC (Min) (V)|
|VCC (Max) (V)|
|Voltage (Nom) (V)|
|F @ Nom Voltage (Max) (Mhz)|
|ICC @ Nom Voltage (Max) (mA)|
|tpd @ Nom Voltage (Max) (ns)|
|Output Drive (IOL/IOH) (Max) (mA)|
|Operating Temperature Range (C)|
|3.3|| 1.8 |
| 1.8 |
| 1.8 |
|12 8.5 6 5|| 18.3 |
| 12 |
| 14.4 |
|-40 to 125||-40 to 125|| -40 to 125 |
-40 to 85
|-40 to 125|
|5SC70|| 6SC70 |
| 5DSBGA |
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