SN74LVC1G79-Q1 Single Positive-Edge-Triggered D-Type Flip-Flop
SCES874 – March2017
- Qualified for Automotive Applications
- AEC-Q100 Qualified With the Following Results:
- ±4000-V Human-Body Model (HBM) ESD Classification Level 3A
- ±1000-V Charged-Device Model (CDM) ESD Classification Level C5
- Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Supports Down Translation to VCC
- Max tpd of 6 ns at 3.3 V and 50 pF load
- Low Power Consumption, 10-µA Max ICC
- ±24-mA Output Drive at 3.3 V
- Ioff supports Partial-Power-Down Mode and Back-Drive Protection
- Automotive Infotainment
- Automotive Cluster
- Automotive ADAS
- Automotive Body Electronics
- Automotive HEV/EV Powertrain
This automotive AEC-Q100 qualified single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
|PART NUMBER||PACKAGE||BODY SIZE|
|SN74LVC1G79QDCKRQ1||SC70 (5)||2.00 mm × 1.25 mm|
- For all available packages, see the orderable addendum at the end of the data sheet.
Logic Diagram (Positive Logic)
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