SN74LVC8T245 8-Bit Dual-Supply Bus Transceiver with Configurable Voltage-Level Shifting and Three-State Outputs | TI.com

SN74LVC8T245 (ACTIVE)

8-Bit Dual-Supply Bus Transceiver with Configurable Voltage-Level Shifting and Three-State Outputs

 

Description

This 8-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74LVC8T245 is optimized to operate with VCCA and VCCB set at 1.65 V to 5.5 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5.5-V voltage nodes.

The SN74LVC8T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC8T245 is designed so that the control pins (DIR and OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, all outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Features

  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input Is at GND, All Are in the High-Impedance State
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 100-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

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Parametrics Compare all products in Direction controlled voltage translation

 
Technology Family
Application
Bits (#)
High input voltage (Min) (Vih)
High input voltage (Max) (Vih)
Output voltage (Min) (V)
Output voltage (Max) (V)
IOH (Max) (mA)
IOL (Max) (mA)
Package Group
Rating
SN74LVC8T245 SN74AVC8T245 SN74AVC8T245-Q1 SN74AXC8T245 SN74AXCH8T245 SN74LVC8T245-Q1 TXB0108 TXS0108E
LVC     AVC     AVC     AXC     AXC     LVC     TXB     TXS    
RGMII
SPI
JTAG    
UART
SPI
JTAG
I2S    
UART
SPI
JTAG
I2S    
RGMII
SPI
UART
JTAG
I2S    
RGMII
SPI
UART
JTAG
I2S    
RGMII
SPI
JTAG    
SPI
I2C
SDIO    
I2C
SMBUS
UART
GPIO    
8     8     8     8     8     8     8     8    
1.08     0.78     0.78     0.455     0.455     1.08     0.78     1    
5.5     3.6     3.6     3.6     3.6     5.5     5.5     5.5    
1.65     1.2     1.2     0.65     0.65     1.65     1.2     1.2    
5.5     3.6     3.6     3.6     3.6     5.5     5.5     5.5    
-32     -12     -12     -12     -12     -32     -0.02     0    
32     12     12     12     12     32     0.02     0    
SOIC | 24
SO | 24
SSOP | 24
SSOP | 24
TSSOP | 24
TVSOP | 24
VQFN | 24    
TSSOP | 24
TVSOP | 24
VQFN | 24    
TSSOP | 24
VQFN | 24    
TSSOP | 24
UQFN | 24
VQFN | 24    
TSSOP | 24
VQFN | 24    
TSSOP | 24     BGA MICROSTAR JUNIOR | 20
DSBGA | 20
TSSOP | 20
USON | 20
VQFN | 20    
BGA MICROSTAR JUNIOR | 20
TSSOP | 20
VQFN | 20    
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Design tool

WEBENCH® SN74LVC8T245

Tx:
Mid Channel:
Rx:
Max Data Rate: Gbps
Number of UI:
PRBS:
Eye Diagram