These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the '175, 'LS175, and 'S175 feature complementary outputs from each flip-flop.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
|Part number||Order||Technology Family||Input type||Output type||VCC (Min) (V)||VCC (Max) (V)||Channels (#)||Clock Frequency (Max) (MHz)||ICC (uA)||IOL (Max) (mA)||IOH (Max) (mA)||Features||Rating||Package Group|
||S||Bipolar||Push-Pull||4.75||5.25||4||50||96000||20||-1||High speed (tpd 10-50ns)||Catalog||
PDIP | 16
SOIC | 16
|SN54S175||Samples not available||S||Bipolar||Push-Pull||4.75||5.25||4||50||96000||20||-1||High speed (tpd 10-50ns)||Military||CDIP | 16|