On-State Connection Between Ports A and BThe SN74TVC3010 provides 11 parallel NMOS pass transistors with a common gate. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.
The device can be used as a 10-bit switch with the gates cascaded together to a reference transistor. The low-voltage side of each pass transistor is limited to a voltage set by the reference transistor. This is done to protect components with inputs that are sensitive to high-state voltage-level overshoots. (See Application Information in this data sheet.)
All of the transistors in the TVC array have the same electrical characteristics; therefore, any one of them can be used as the reference transistor. Since, within the device, the characteristics from transistor to transistor are equal, the maximum output high-state voltage (VOH) is approximately the reference voltage (VREF), with minimal deviation from one output to another. This is a large benefit of the TVC solution over discrete devices. Because the fabrication of the transistors is symmetrical, either port connection of each bit can be used as the low-voltage side, and the I/O signals are bidirectional through each FET.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | SN74TVC3010 datasheet (Rev. G) | 27 Aug 2003 | |
| Application note | Selecting the Correct Texas Instruments Signal Switch (Rev. E) | PDF | HTML | 02 Jun 2022 | |
| Application note | Multiplexers and Signal Switches Glossary (Rev. B) | PDF | HTML | 01 Dec 2021 | |
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dec 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
| Application note | Selecting the Right Level Translation Solution (Rev. A) | 22 Jun 2004 | ||
| User guide | Signal Switch Data Book (Rev. A) | 14 Nov 2003 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 Aug 2002 | ||
| More literature | Standard Linear & Logic for PCs, Servers & Motherboards | 13 Jun 2002 |
For additional terms or required resources, click any title below to view the detail page where available.
The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages. The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.
| Package | Pins | Download |
|---|---|---|
| SOIC (DW) | 24 | View options |
| SSOP (DBQ) | 24 | View options |
| TSSOP (PW) | 24 | View options |
| TVSOP (DGV) | 24 | View options |
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