SLASEM6A October 2017  – December 2017 TAS2770

PRODUCTION DATA. 

  1. 1     Features
  2. 2     Applications
  3. 3     Description
  4. DeviceImages
    1. 3.1Functional Block Diagram
  5. 4     Revision History
  6. 5     Pin Configuration and Functions
    1. PinFunctions
  7. 6     Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6I2C Timing Requirements
    7. 6.7TDM Port Timing Requirements
    8. 6.8PDM Port Timing Requirements
    9. 6.9Typical Characteristics
  8. 7     Parameter Measurement Information
  9. 8     Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1Device Mode and Address Selection
      2. 8.3.2General I2C Operation
      3. 8.3.3Single-Byte and Multiple-Byte Transfers
      4. 8.3.4Single-Byte Write
      5. 8.3.5Multiple-Byte Write and Incremental Multiple-Byte Write
      6. 8.3.6Single-Byte Read
      7. 8.3.7Multiple-Byte Read
      8. 8.3.8Register Organization
    4. 8.4Device Functional Modes
      1. 8.4.1PDM Input
      2. 8.4.2TDM Port
      3. 8.4.3Playback Signal Path
        1. 8.4.3.1High Pass Filter
        2. 8.4.3.2Digital Volume Control and Amplifier Output Level
        3. 8.4.3.3 Audio Playback Selection
        4. 8.4.3.4Battery Tracking Limiter with Brown Out Prevention
        5. 8.4.3.5Inter Chip Limiter Alignment
          1. 8.4.3.5.1TDM Mode
        6. 8.4.3.6Class-D Settings
      4. 8.4.4 SAR ADC
      5. 8.4.5IV Sense
      6. 8.4.6Clocks and PLL
    5. 8.5Operational Modes
      1. 8.5.1Hardware Shutdown
      2. 8.5.2Software Shutdown
      3. 8.5.3Mute
      4. 8.5.4Active
      5. 8.5.5Mode Control and Software Reset
    6. 8.6Faults and Status
    7. 8.7Power Sequencing Requirements
    8. 8.8Digital Input Pull Downs
    9. 8.9Register Maps
      1. 8.9.1Register Summary Table Book=0x00 Page=0x00
      2. 8.9.2Register Maps
        1. 8.9.2.1 PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
          1. Table83. Device Page Field Descriptions
        2. 8.9.2.2 SW_RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
          1. Table84. Software Reset Field Descriptions
        3. 8.9.2.3 PWR_CTL (book=0x00 page=0x00 address=0x02) [reset=Eh]
          1. Table85. Power Control Field Descriptions
        4. 8.9.2.4 PB_CFG0 (book=0x00 page=0x00 address=0x03) [reset=10h]
          1. Table86. Playback Configuration 0 Field Descriptions
        5. 8.9.2.5 PB_CFG1 (book=0x00 page=0x00 address=0x04) [reset=1h]
          1. Table87. Playback Configuration 1 Field Descriptions
        6. 8.9.2.6 PB_CFG2 (book=0x00 page=0x00 address=0x05) [reset=0h]
          1. Table88. Playback Configuration 2 Field Descriptions
        7. 8.9.2.7 PB_CFG3 (book=0x00 page=0x00 address=0x06) [reset=0h]
          1. Table89. Playback Configuration 3 Field Descriptions
        8. 8.9.2.8 MISC_CFG (book=0x00 page=0x00 address=0x07) [reset=6h]
          1. Table90. Misc Configuration Field Descriptions
        9. 8.9.2.9 PDM_CFG0 (book=0x00 page=0x00 address=0x08) [reset=0h]
          1. Table91. PDM Input Register 0 Field Descriptions
        10. 8.9.2.10PDM_CFG1 (book=0x00 page=0x00 address=0x09) [reset=8h]
          1. Table92. PDM Configuration 1 Field Descriptions
        11. 8.9.2.11TDM_CFG0 (book=0x00 page=0x00 address=0x0A) [reset=7h]
          1. Table93. TDM Configuration 0 Field Descriptions
        12. 8.9.2.12TDM_CFG1 (book=0x00 page=0x00 address=0x0B) [reset=2h]
          1. Table94. TDM Configuration 1 Field Descriptions
        13. 8.9.2.13TDM_CFG2 (book=0x00 page=0x00 address=0x0C) [reset=Ah]
          1. Table95. TDM Configuration 2 Field Descriptions
        14. 8.9.2.14TDM_CFG3 (book=0x00 page=0x00 address=0x0D) [reset=10h]
          1. Table96. TDM Configuration 3 Field Descriptions
        15. 8.9.2.15TDM_CFG4 (book=0x00 page=0x00 address=0x0E) [reset=13h]
          1. Table97. TDM Configuration 4 Field Descriptions
        16. 8.9.2.16TDM_CFG5 (book=0x00 page=0x00 address=0x0F) [reset=2h]
          1. Table98. TDM Configuration 5 Field Descriptions
        17. 8.9.2.17TDM_CFG6 (book=0x00 page=0x00 address=0x10) [reset=0h]
          1. Table99. TDM Configuration 6 Field Descriptions
        18. 8.9.2.18TDM_CFG7 (book=0x00 page=0x00 address=0x11) [reset=4h]
          1. Table100. TDM Configuration 7 Field Descriptions
        19. 8.9.2.19TDM_CFG8 (book=0x00 page=0x00 address=0x12) [reset=6h]
          1. Table101. TDM Configuration 8 Field Descriptions
        20. 8.9.2.20TDM_CFG9 (book=0x00 page=0x00 address=0x13) [reset=7h]
          1. Table102. TDM Configuration 9 Field Descriptions
        21. 8.9.2.21TDM_CFG10 (book=0x00 page=0x00 address=0x14) [reset=8h]
          1. Table103. TDM Configuration 10 Field Descriptions
        22. 8.9.2.22LIM_CFG0 (book=0x00 page=0x00 address=0x15) [reset=14h]
          1. Table104. Limiter Configuration 0 Field Descriptions
        23. 8.9.2.23LIM_CFG1 (book=0x00 page=0x00 address=0x16) [reset=76h]
          1. Table105. Limiter Configuration 1 Field Descriptions
        24. 8.9.2.24LIM_CFG2 (book=0x00 page=0x00 address=0x17) [reset=10h]
          1. Table106. Limiter Configuration 2 Field Descriptions
        25. 8.9.2.25LIM_CFG3 (book=0x00 page=0x00 address=0x18) [reset=6Eh]
          1. Table107. Limiter Configuration 3 Field Descriptions
        26. 8.9.2.26LIM_CFG4 (book=0x00 page=0x00 address=0x19) [reset=1Eh]
          1. Table108. Limiter Configuration 4 Field Descriptions
        27. 8.9.2.27LIM_CFG5 (book=0x00 page=0x00 address=0x1A) [reset=58h]
          1. Table109. Limiter Configuration 5 Field Descriptions
        28. 8.9.2.28BOP_CFG0 (book=0x00 page=0x00 address=0x1B) [reset=1h]
          1. Table110. Brown Out Prevention 0 Field Descriptions
        29. 8.9.2.29BOP_CFG1 (book=0x00 page=0x00 address=0x1C) [reset=14h]
          1. Table111. Brown Out Prevention 1 Field Descriptions
        30. 8.9.2.30BOP_CFG2 (book=0x00 page=0x00 address=0x1D) [reset=4Eh]
          1. Table112. Brown Out Prevention 2 Field Descriptions
        31. 8.9.2.31ICLA_CFG0 (book=0x00 page=0x00 address=0x1E) [reset=0h]
          1. Table113. Inter Chip Limiter Alignment 0 Field Descriptions
        32. 8.9.2.32ICLA_CFG1 (book=0x00 page=0x00 address=0x1F) [reset=0h]
          1. Table114. Inter Chip Limiter Alignment 1 Field Descriptions
        33. 8.9.2.33INT_MASK0 (book=0x00 page=0x00 address=0x20) [reset=FCh]
          1. Table115. Interrupt Mask 0 Field Descriptions
        34. 8.9.2.34INT_MASK1 (book=0x00 page=0x00 address=0x21) [reset=B1h]
          1. Table116. Interrupt Mask 1 Field Descriptions
        35. 8.9.2.35INT_LIVE0 (book=0x00 page=0x00 address=0x22) [reset=0h]
          1. Table117. Live Interrupt Readback 0 Field Descriptions
        36. 8.9.2.36INT_LIVE1 (book=0x00 page=0x00 address=0x23) [reset=0h]
          1. Table118. Live Interrupt Readback 1 Field Descriptions
        37. 8.9.2.37INT_LTCH0 (book=0x00 page=0x00 address=0x24) [reset=0h]
          1. Table119. Latched Interrupt Readback 0 Field Descriptions
        38. 8.9.2.38INT_LTCH1 (book=0x00 page=0x00 address=0x25) [reset=0h]
          1. Table120. Latched Interrupt Readback 1 Field Descriptions
        39. 8.9.2.39INT_LTCH2 (book=0x00 page=0x00 address=0x26) [reset=0h]
          1. Table1. INT_LTCH2 Register Address: 0x26
          2. Table121. INT_LTCH2 Field Descriptions
        40. 8.9.2.40VBAT_MSB (book=0x00 page=0x00 address=0x27) [reset=0h]
          1. Table122. SAR ADC Conversion 0 Field Descriptions
        41. 8.9.2.41VBAT_LSB (book=0x00 page=0x00 address=0x28) [reset=0h]
          1. Table123. SAR ADC Conversion 1 Field Descriptions
        42. 8.9.2.42TEMP_MSB (book=0x00 page=0x00 address=0x29) [reset=0h]
          1. Table124. SAR ADC Conversion 2 Field Descriptions
        43. 8.9.2.43TEMP_LSB (book=0x00 page=0x00 address=0x2A) [reset=0h]
          1. Table125. SAR ADC Conversion 2 Field Descriptions
        44. 8.9.2.44INT_CFG (book=0x00 page=0x00 address=0x30) [reset=5h]
          1. Table126. Interrupt Configuration Field Descriptions
        45. 8.9.2.45DIN_PD (book=0x00 page=0x00 address=0x31) [reset=0h]
          1. Table127. Digital Input Pin Pull Down Field Descriptions
        46. 8.9.2.46MISC_IRQ (book=0x00 page=0x00 address=0x32) [reset=81h]
          1. Table128. Misc Configuration Field Descriptions
        47. 8.9.2.47CLOCK_CFG (book=0x00 page=0x00 address=0x3C) [reset=Dh]
          1. Table129. Clock Configuration Field Descriptions
        48. 8.9.2.48TDM_DET (book=0x00 page=0x00 address=0x77) [reset=7Fh]
          1. Table130. TDM Clock detection monitor Field Descriptions
        49. 8.9.2.49REV_ID (book=0x00 page=0x00 address=0x7D) [reset=20h]
          1. Table131. Revision and PG ID Field Descriptions
        50. 8.9.2.50I2C_CKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]
          1. Table132. I2C Checksum Field Descriptions
        51. 8.9.2.51BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
          1. Table133. Device Book Field Descriptions
  10. 9     Application and Implementation
    1. 9.1Application Information
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
      2. 9.2.2Detailed Design Procedure
        1. 9.2.2.1Overview
        2. 9.2.2.2Select Input Capacitance
        3. 9.2.2.3Select Decoupling Capacitors
        4. 9.2.2.4Select Bootstrap Capacitors
      3. 9.2.3Application Curves
    3. 9.3Initialization Set Up
      1. 9.3.1Initial Device Configuration - Auto Rate
      2. 9.3.2Initial Device Configuration - 48 kHz
      3. 9.3.3Initial Device Configuration - 44.1 kHz
      4. 9.3.4Sample Rate Change - 48 kHz to 44.1kHz
      5. 9.3.5Sample Rate Change - 44.1 kHz to 48 kHz
      6. 9.3.6Device Mute
      7. 9.3.7Device Un-Mute
      8. 9.3.8Device Sleep
      9. 9.3.9Device Wake
  11. 10    Power Supply Recommendations
  12. 11    Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  13. 12    Device and Documentation Support
    1. 12.1Receiving Notification of Documentation Updates
    2. 12.2Community Resources
    3. 12.3Trademarks
    4. 12.4Electrostatic Discharge Caution
    5. 12.5Glossary
  14. 13    Mechanical, Packaging, and Orderable Information
    1. 13.1Package Option Addendum
      1. 13.1.1Packaging Information
      2. 13.1.2Tape and Reel Information

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The TAS2770 is a digital input Class-D audio power amplifier with integrated I/V sense. I2S audio data is supplied by host processor. It also accepts I/V data in I2S format. I2C bus is used for configuration and control.

Typical Application

Figure 105 below shows a typical configuration of the TAS2770.

TAS2770 apps_diagram_digital_input_tas2770.gif Figure 105. TAS2770 Typical Application

Design Requirements

Table 134 shows the design parameters.

Table 134. Recommended Component Selection

PARAMETEREXAMPLE VALUE
Amplifier power supply (VBAT) 4.5 V to 16 V
EVM power supply4.5 V to 16 V
IO power supply (IOVDD)1.65 V to 1.95 V
Output Power18.3 W
USB, USB class-audio Micro-USB B

Detailed Design Procedure

Overview

The TAS2770 is a flexible and easy-to-use Class D amplifier. Therefore, the design process is straightforward.

Before beginning the design, gather the following information regarding the audio system:

  • VBAT rail planned for the design
  • Speaker or load impedance
  • Audio sample rate
  • Maximum output power requirement

Select Input Capacitance

Select the bulk capacitors at the VBAT inputs for proper voltage margin and adequate capacitance to support the power requirements. The TAS2770 has very good PSRR, so the capacitor is more about limiting the ripple and droop for the rest of system than preserving good audio performance. The amount of bulk decoupling can be reduced as long as the droop and ripple is acceptable. One capacitor should be placed near the VBAT pin. VBATY capacitors should be a low ESR type because they are being used in a high-speed switching application.

Select Decoupling Capacitors

Good quality decoupling capacitors should be added at each of the VBAT input to provide good reliability, good audio performance, and to meet regulatory requirements. X5R or better ratings should be used in this application. Consider temperature, ripple current, and voltage overshoots when selecting decoupling capacitors.

Also, the decoupling capacitors should be located near the VBAT and GND connections to the device to minimize series inductances.

Select Bootstrap Capacitors

Each of the outputs require bootstrap capacitors to provide gate drive for the high-side output FETs. For this design, use 0.1-µF, 25-V capacitors of X5R quality or better.

Application Curves

TAS2770 D002_SLASEM6.gif Figure 106. THD+N vs Frequency
TAS2770 D003_SLASEM6.gif Figure 107. THD+N vs Output Power (W)

Initialization Set Up

Initial Device Configuration - Auto Rate

The following I2C sequence is an example of initializing four TAS2770 devices. The devices will be configured to use the TDM auto-rate detection feature. This sequence contains a 1 ms delay required after a software or hardware reset as illustrated in Power Supply Recommendations.

w 62 00 00 # Page-0w 62 7f 00 # Book-0w 62 01 01 # Software Resetw 64 00 00 # Page-0w 64 7f 00 # Book-0w 64 01 01 # Software Resetw 66 00 00 # Page-0w 66 7f 00 # Book-0w 66 01 01 # Software Resetw 68 00 00 # Page-0w 68 7f 00 # Book-0w 68 01 01 # Software Resetd 1 # 1mS Delay###### Configure Channel 1w 62 3c 11 # sbclk to fs ratio = 64w 62 0e 33 # TX bus keeper, Hi-Z, offset 1, TX on Falling edgew 62 0f 42 # TDM TX voltage sense transmit enable with slot 2, w 62 10 40 # TDM TX current sense transmit enable with slot 0w 62 03 14 # 21 dB gainw 62 02 00 # power up audio playback with I,V enabled###### Configure Channel 2w 64 3c 11 # sbclk to fs ratio = 64w 64 0e 13 # TX bus keeper, Hi-Z, offset 1, TX on Falling edgew 64 0f 46 # TDM TX voltage sense transmit enable with slot 6, w 64 10 44 # TDM TX current sense transmit enable with slot 4w 64 03 14 # 21 dB gainw 64 02 00 # power up audio playback with I,V enabled###### Configure Channel 3w 66 3c 11 # sbclk to fs ratio = 64w 66 0e 13 # TX bus keeper, Hi-Z, offset 1, TX on Falling edgew 66 0f 4A # TDM TX voltage sense transmit enable with slot 10, w 66 10 48 # TDM TX current sense transmit enable with slot 8w 66 03 14 # 21 dB gainw 66 02 00 # power up audio playback with I,V enabled###### Configure Channel 4w 68 3c 11 # sbclk to fs ratio = 64w 68 0e 13 # TX bus keeper, Hi-Z, offset 1, TX on Falling edgew 68 0f 4E # TDM TX voltage sense transmit enable with slot 14, w 68 10 4C # TDM TX current sense transmit enable with slot 12w 68 03 14 # 21 dB gainw 68 02 00 # power up audio playback with I,V enabled

Initial Device Configuration - 48 kHz

The following I2C sequence is an example of initializing a TAS2770 device into 48 kHz sampling rate. This sequence contains a 1 ms delay required after a software or hardware reset as illustrated in Power Supply Recommendations.

w 62 00 00 # Page-0w 62 7f 00 # Book-0w 62 01 01 # Software Resetd 1 # 1mS Delay###### Configure Channel 1w 62 3c 21 # sbclk to fs ratio = 256 / 8 TDM Slotsw 62 0a 17 # 48KHz, Auto TDM off, Frame start High to Loww 62 0b 03 # Offset = 1, Sync on BCLK falling edgew 62 0c 0a # TDM slot by address, Word = 24 bit, Frame = 32 bitw 62 0d 20 # Right Ch = TDM slot 2, Left Ch = TDM slot 0w 62 0e 33 # TX bus keeper, Hi-Z, offset 1, TX on Falling edgew 62 0f 42 # TDM TX voltage sense transmit enable with slot 2, w 62 10 40 # TDM TX current sense transmit enable with slot 0w 62 03 14 # 21 dB gainw 62 02 00 # power up audio playback with I,V enabled

Initial Device Configuration - 44.1 kHz

The following I2C sequence is an example of initializing a TAS2770 device into 48 kHz sampling rate. This sequence contains a 1 ms delay required after a software or hardware reset as illustrated in Power Supply Recommendations.

w 62 00 00 # Page-0w 62 7f 00 # Book-0w 62 01 01 # Software Resetd 1 # 1mS Delay###### Configure Channel 1w 62 3c 21 # sbclk to fs ratio = 256 / 8 TDM Slotsw 62 0a 37 # 44.1KHz, Auto TDM off, Frame start High to Loww 62 0b 03 # Offset = 1, Sync on BCLK falling edgew 62 0c 0a # TDM slot by address, Word = 24 bit, Frame = 32 bitw 62 0d 20 # Right Ch = TDM slot 2, Left Ch = TDM slot 0w 62 0e 33 # TX bus keeper, Hi-Z, offset 1, TX on Falling edgew 62 0f 42 # TDM TX voltage sense transmit enable with slot 2, w 62 10 40 # TDM TX current sense transmit enable with slot 0w 62 03 14 # 21 dB gainw 62 02 00 # power up audio playback with I,V enabled

Sample Rate Change - 48 kHz to 44.1kHz

The following I2C sequence is an example of changing the sampling rate from 48 kHz to 44.1 kHz .

w 62 07 80 #Set DVC Ramp Rate to 0.5 dB / 8 samplesw 62 02 01 #Muted 1w 62 02 02 #Software shutdownw 62 0a 37 #44.1KHz, Auto TDM off, Frame start High to Low### change source sample rate noww 62 02 01 #Take device out of low-power shutdownd 1w 62 02 00 #Un-mute

Sample Rate Change - 44.1 kHz to 48 kHz

The following I2C sequence is an example of changing the sampling rate from 44.1 kHz to 48 kHz .

w 62 07 80 #Set DVC Ramp Rate to 0.5 dB / 8 samplesw 62 02 01 #Muted 1w 62 02 02 #Software shutdownw 62 0a 17 #44.1KHz, Auto TDM off, Frame start High to Low### change source sample rate noww 62 02 01 #Take device out of low-power shutdownd 1w 62 02 00 #Un-mute

Device Mute

The following I2C sequence will mute one device at address 62 using a digital volume ramp rate of 0.5dB per 8 samples.

w 62 07 80 #Set DVC Ramp Rate to 0.5 dB / 8 samplesw 62 02 01 #Mute

Device Un-Mute

The following I2C sequence will un-mute one device at address 62 using a digital volume ramp rate of 0.5dB per 8 samples.

w 62 07 80 #Set DVC Ramp Rate to 0.5 dB / 8 samplesw 62 02 00 #Un-Mute

Device Sleep

The following I2C sequence will mute the device and put it into low power mode for one device at address 62 using a digital volume ramp rate of 0.5dB per 8 samples.

w 62 07 80 #Set DVC Ramp Rate to 0.5 dB / 8 samplesw 62 02 01 #Muted 1 # 1mS Delayw 62 02 02 #Software shutdown

Device Wake

The following I2C sequence will wake the device from low power mode (sleep) and un-mute one device at address 62 using a digital volume ramp rate of 0.5dB per 8 samples.

w 62 07 80 #Set DVC Ramp Rate to 0.5 dB / 8 samplesw 62 02 01 #Take device out of low-power shutdownd 1 # 1mS Delayw 62 02 00 #Un-mute TAS2770