SLASEM6A October 2017  – December 2017 TAS2770

PRODUCTION DATA. 

  1. 1     Features
  2. 2     Applications
  3. 3     Description
  4. DeviceImages
    1. 3.1Functional Block Diagram
  5. 4     Revision History
  6. 5     Pin Configuration and Functions
    1. PinFunctions
  7. 6     Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6I2C Timing Requirements
    7. 6.7TDM Port Timing Requirements
    8. 6.8PDM Port Timing Requirements
    9. 6.9Typical Characteristics
  8. 7     Parameter Measurement Information
  9. 8     Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1Device Mode and Address Selection
      2. 8.3.2General I2C Operation
      3. 8.3.3Single-Byte and Multiple-Byte Transfers
      4. 8.3.4Single-Byte Write
      5. 8.3.5Multiple-Byte Write and Incremental Multiple-Byte Write
      6. 8.3.6Single-Byte Read
      7. 8.3.7Multiple-Byte Read
      8. 8.3.8Register Organization
    4. 8.4Device Functional Modes
      1. 8.4.1PDM Input
      2. 8.4.2TDM Port
      3. 8.4.3Playback Signal Path
        1. 8.4.3.1High Pass Filter
        2. 8.4.3.2Digital Volume Control and Amplifier Output Level
        3. 8.4.3.3 Audio Playback Selection
        4. 8.4.3.4Battery Tracking Limiter with Brown Out Prevention
        5. 8.4.3.5Inter Chip Limiter Alignment
          1. 8.4.3.5.1TDM Mode
        6. 8.4.3.6Class-D Settings
      4. 8.4.4 SAR ADC
      5. 8.4.5IV Sense
      6. 8.4.6Clocks and PLL
    5. 8.5Operational Modes
      1. 8.5.1Hardware Shutdown
      2. 8.5.2Software Shutdown
      3. 8.5.3Mute
      4. 8.5.4Active
      5. 8.5.5Mode Control and Software Reset
    6. 8.6Faults and Status
    7. 8.7Power Sequencing Requirements
    8. 8.8Digital Input Pull Downs
    9. 8.9Register Maps
      1. 8.9.1Register Summary Table Book=0x00 Page=0x00
      2. 8.9.2Register Maps
        1. 8.9.2.1 PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
          1. Table83. Device Page Field Descriptions
        2. 8.9.2.2 SW_RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
          1. Table84. Software Reset Field Descriptions
        3. 8.9.2.3 PWR_CTL (book=0x00 page=0x00 address=0x02) [reset=Eh]
          1. Table85. Power Control Field Descriptions
        4. 8.9.2.4 PB_CFG0 (book=0x00 page=0x00 address=0x03) [reset=10h]
          1. Table86. Playback Configuration 0 Field Descriptions
        5. 8.9.2.5 PB_CFG1 (book=0x00 page=0x00 address=0x04) [reset=1h]
          1. Table87. Playback Configuration 1 Field Descriptions
        6. 8.9.2.6 PB_CFG2 (book=0x00 page=0x00 address=0x05) [reset=0h]
          1. Table88. Playback Configuration 2 Field Descriptions
        7. 8.9.2.7 PB_CFG3 (book=0x00 page=0x00 address=0x06) [reset=0h]
          1. Table89. Playback Configuration 3 Field Descriptions
        8. 8.9.2.8 MISC_CFG (book=0x00 page=0x00 address=0x07) [reset=6h]
          1. Table90. Misc Configuration Field Descriptions
        9. 8.9.2.9 PDM_CFG0 (book=0x00 page=0x00 address=0x08) [reset=0h]
          1. Table91. PDM Input Register 0 Field Descriptions
        10. 8.9.2.10PDM_CFG1 (book=0x00 page=0x00 address=0x09) [reset=8h]
          1. Table92. PDM Configuration 1 Field Descriptions
        11. 8.9.2.11TDM_CFG0 (book=0x00 page=0x00 address=0x0A) [reset=7h]
          1. Table93. TDM Configuration 0 Field Descriptions
        12. 8.9.2.12TDM_CFG1 (book=0x00 page=0x00 address=0x0B) [reset=2h]
          1. Table94. TDM Configuration 1 Field Descriptions
        13. 8.9.2.13TDM_CFG2 (book=0x00 page=0x00 address=0x0C) [reset=Ah]
          1. Table95. TDM Configuration 2 Field Descriptions
        14. 8.9.2.14TDM_CFG3 (book=0x00 page=0x00 address=0x0D) [reset=10h]
          1. Table96. TDM Configuration 3 Field Descriptions
        15. 8.9.2.15TDM_CFG4 (book=0x00 page=0x00 address=0x0E) [reset=13h]
          1. Table97. TDM Configuration 4 Field Descriptions
        16. 8.9.2.16TDM_CFG5 (book=0x00 page=0x00 address=0x0F) [reset=2h]
          1. Table98. TDM Configuration 5 Field Descriptions
        17. 8.9.2.17TDM_CFG6 (book=0x00 page=0x00 address=0x10) [reset=0h]
          1. Table99. TDM Configuration 6 Field Descriptions
        18. 8.9.2.18TDM_CFG7 (book=0x00 page=0x00 address=0x11) [reset=4h]
          1. Table100. TDM Configuration 7 Field Descriptions
        19. 8.9.2.19TDM_CFG8 (book=0x00 page=0x00 address=0x12) [reset=6h]
          1. Table101. TDM Configuration 8 Field Descriptions
        20. 8.9.2.20TDM_CFG9 (book=0x00 page=0x00 address=0x13) [reset=7h]
          1. Table102. TDM Configuration 9 Field Descriptions
        21. 8.9.2.21TDM_CFG10 (book=0x00 page=0x00 address=0x14) [reset=8h]
          1. Table103. TDM Configuration 10 Field Descriptions
        22. 8.9.2.22LIM_CFG0 (book=0x00 page=0x00 address=0x15) [reset=14h]
          1. Table104. Limiter Configuration 0 Field Descriptions
        23. 8.9.2.23LIM_CFG1 (book=0x00 page=0x00 address=0x16) [reset=76h]
          1. Table105. Limiter Configuration 1 Field Descriptions
        24. 8.9.2.24LIM_CFG2 (book=0x00 page=0x00 address=0x17) [reset=10h]
          1. Table106. Limiter Configuration 2 Field Descriptions
        25. 8.9.2.25LIM_CFG3 (book=0x00 page=0x00 address=0x18) [reset=6Eh]
          1. Table107. Limiter Configuration 3 Field Descriptions
        26. 8.9.2.26LIM_CFG4 (book=0x00 page=0x00 address=0x19) [reset=1Eh]
          1. Table108. Limiter Configuration 4 Field Descriptions
        27. 8.9.2.27LIM_CFG5 (book=0x00 page=0x00 address=0x1A) [reset=58h]
          1. Table109. Limiter Configuration 5 Field Descriptions
        28. 8.9.2.28BOP_CFG0 (book=0x00 page=0x00 address=0x1B) [reset=1h]
          1. Table110. Brown Out Prevention 0 Field Descriptions
        29. 8.9.2.29BOP_CFG1 (book=0x00 page=0x00 address=0x1C) [reset=14h]
          1. Table111. Brown Out Prevention 1 Field Descriptions
        30. 8.9.2.30BOP_CFG2 (book=0x00 page=0x00 address=0x1D) [reset=4Eh]
          1. Table112. Brown Out Prevention 2 Field Descriptions
        31. 8.9.2.31ICLA_CFG0 (book=0x00 page=0x00 address=0x1E) [reset=0h]
          1. Table113. Inter Chip Limiter Alignment 0 Field Descriptions
        32. 8.9.2.32ICLA_CFG1 (book=0x00 page=0x00 address=0x1F) [reset=0h]
          1. Table114. Inter Chip Limiter Alignment 1 Field Descriptions
        33. 8.9.2.33INT_MASK0 (book=0x00 page=0x00 address=0x20) [reset=FCh]
          1. Table115. Interrupt Mask 0 Field Descriptions
        34. 8.9.2.34INT_MASK1 (book=0x00 page=0x00 address=0x21) [reset=B1h]
          1. Table116. Interrupt Mask 1 Field Descriptions
        35. 8.9.2.35INT_LIVE0 (book=0x00 page=0x00 address=0x22) [reset=0h]
          1. Table117. Live Interrupt Readback 0 Field Descriptions
        36. 8.9.2.36INT_LIVE1 (book=0x00 page=0x00 address=0x23) [reset=0h]
          1. Table118. Live Interrupt Readback 1 Field Descriptions
        37. 8.9.2.37INT_LTCH0 (book=0x00 page=0x00 address=0x24) [reset=0h]
          1. Table119. Latched Interrupt Readback 0 Field Descriptions
        38. 8.9.2.38INT_LTCH1 (book=0x00 page=0x00 address=0x25) [reset=0h]
          1. Table120. Latched Interrupt Readback 1 Field Descriptions
        39. 8.9.2.39INT_LTCH2 (book=0x00 page=0x00 address=0x26) [reset=0h]
          1. Table1. INT_LTCH2 Register Address: 0x26
          2. Table121. INT_LTCH2 Field Descriptions
        40. 8.9.2.40VBAT_MSB (book=0x00 page=0x00 address=0x27) [reset=0h]
          1. Table122. SAR ADC Conversion 0 Field Descriptions
        41. 8.9.2.41VBAT_LSB (book=0x00 page=0x00 address=0x28) [reset=0h]
          1. Table123. SAR ADC Conversion 1 Field Descriptions
        42. 8.9.2.42TEMP_MSB (book=0x00 page=0x00 address=0x29) [reset=0h]
          1. Table124. SAR ADC Conversion 2 Field Descriptions
        43. 8.9.2.43TEMP_LSB (book=0x00 page=0x00 address=0x2A) [reset=0h]
          1. Table125. SAR ADC Conversion 2 Field Descriptions
        44. 8.9.2.44INT_CFG (book=0x00 page=0x00 address=0x30) [reset=5h]
          1. Table126. Interrupt Configuration Field Descriptions
        45. 8.9.2.45DIN_PD (book=0x00 page=0x00 address=0x31) [reset=0h]
          1. Table127. Digital Input Pin Pull Down Field Descriptions
        46. 8.9.2.46MISC_IRQ (book=0x00 page=0x00 address=0x32) [reset=81h]
          1. Table128. Misc Configuration Field Descriptions
        47. 8.9.2.47CLOCK_CFG (book=0x00 page=0x00 address=0x3C) [reset=Dh]
          1. Table129. Clock Configuration Field Descriptions
        48. 8.9.2.48TDM_DET (book=0x00 page=0x00 address=0x77) [reset=7Fh]
          1. Table130. TDM Clock detection monitor Field Descriptions
        49. 8.9.2.49REV_ID (book=0x00 page=0x00 address=0x7D) [reset=20h]
          1. Table131. Revision and PG ID Field Descriptions
        50. 8.9.2.50I2C_CKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]
          1. Table132. I2C Checksum Field Descriptions
        51. 8.9.2.51BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
          1. Table133. Device Book Field Descriptions
  10. 9     Application and Implementation
    1. 9.1Application Information
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
      2. 9.2.2Detailed Design Procedure
        1. 9.2.2.1Overview
        2. 9.2.2.2Select Input Capacitance
        3. 9.2.2.3Select Decoupling Capacitors
        4. 9.2.2.4Select Bootstrap Capacitors
      3. 9.2.3Application Curves
    3. 9.3Initialization Set Up
      1. 9.3.1Initial Device Configuration - Auto Rate
      2. 9.3.2Initial Device Configuration - 48 kHz
      3. 9.3.3Initial Device Configuration - 44.1 kHz
      4. 9.3.4Sample Rate Change - 48 kHz to 44.1kHz
      5. 9.3.5Sample Rate Change - 44.1 kHz to 48 kHz
      6. 9.3.6Device Mute
      7. 9.3.7Device Un-Mute
      8. 9.3.8Device Sleep
      9. 9.3.9Device Wake
  11. 10    Power Supply Recommendations
  12. 11    Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  13. 12    Device and Documentation Support
    1. 12.1Receiving Notification of Documentation Updates
    2. 12.2Community Resources
    3. 12.3Trademarks
    4. 12.4Electrostatic Discharge Caution
    5. 12.5Glossary
  14. 13    Mechanical, Packaging, and Orderable Information
    1. 13.1Package Option Addendum
      1. 13.1.1Packaging Information
      2. 13.1.2Tape and Reel Information

Detailed Description

Overview

The TAS2770 is a mono digital input Class-D amplifier optimized for mobile applications where efficient battery operation and small solution size are crucial. It integrates speaker voltage and current sensing and battery tracking limiting with brown out prevention. The device can operate in either TDM/I2C mode. Both modes support two PDM inputs that can be used for low latency playback or sensor aggregation.

Functional Block Diagram

TAS2770 block_diagram_slasei8.gif

Feature Description

Device Mode and Address Selection

The TAS2770 can operate in two distinct operational modes, each with eight selectable device addresses. In TDM/I2C Mode, audio input and output are provided via the FSYNC, SBCLK, SDIN and SDOUT pins using formats including I2S, Left Justified and TDM. Configuration and status are provided via the SDA and SCL pins using the I2C protocol.

The PDM input can be used for a low latency playback path or as a sensor input.

Table 2 below illustrates how to configure the device for TDM/I2C Mode. I2C slave addresses are shown left shifted by one bit with the R/W bit set to 0 (i.e. \{ADDR[6:0],1b0\}). 5% or better tolerance resistors should be used for setting the mode configuration.

Table 2. TDM/I2C Mode Address Selection

MODE PINI2C SLAVE ADDRESS
TAS2770
Short to GND0x82
470 Ω to GND0X84
470 Ω to IOVDD0x86
2.2 KΩ to GND0x88
2.2 KΩ to IOVDD0x8A
10 KΩ to GND0x8C
10 KΩ to IOVDD0x8E
47 KΩ to IOVDD0x90

General I2C Operation

The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system using serial data transmission. The address and data 8-bit bytes are transferred most-significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. shows a typical sequence.

The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The device holds SDA low during the acknowledge clock period to indicate acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bi-directional bus using a wired-AND connection.

Use external pull-up resistors for the SDA and SCL signals to set the logic-high level for the bus. Use pull-up resistors between 2 kΩ and 4.7 kΩ. Do not allow the SDA and SCL voltages to exceed the device supply voltage, IOVDD.

TAS2770 i2c_seq_los492.gif Figure 37. Typical I2C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. Figure 37shows a generic data transfer sequence.

Single-Byte and Multiple-Byte Transfers

The serial control interface supports both single-byte and multiple-byte read/write operations for all registers. During multiple-byte read operations, the TAS2770 responds with data, a byte at a time, starting at the register assigned, as long as the master device continues to respond with acknowledges.

The TAS2770 supports sequential I2C addressing. For write transactions, if a register is issued followed by data for that register and all the remaining registers that follow, a sequential I2C write transaction has taken place. For I2C sequential write transactions, the register issued then serves as the starting point, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines to how many registers are written.

Single-Byte Write

As shown in Figure 38, a single-byte data-write transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write-data transfer, the read/write bit must be set to 0. After receiving the correct I2C device address and the read/write bit, the TAS2770 responds with an acknowledge bit. Next, the master transmits the register byte corresponding to the device internal memory address being accessed. After receiving the register byte, the device again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.

TAS2770 sbw_trn_los492.gif Figure 38. Single-Byte Write Transfer

Multiple-Byte Write and Incremental Multiple-Byte Write

A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the TAS2770 as shown in Figure 39. After receiving each data byte, the device responds with an acknowledge bit.

TAS2770 mbw_trn_los492.gif Figure 39. Multi-Byte Write Transfer

Single-Byte Read

As shown in Figure 40, a single-byte data-read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory address to be read. As a result, the read/write bit is set to a 0.

After receiving the TAS2770 address and the read/write bit, the device responds with an acknowledge bit. The master then sends the internal memory address byte, after which the device issues an acknowledge bit. The master device transmits another start condition followed by the TAS2770 address and the read/write bit again. This time, the read/write bit is set to 1, indicating a read transfer. Next, the TAS2770 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.

TAS2770 sbr_trn_los492.gif Figure 40. Single-Byte Read Transfer

Multiple-Byte Read

A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are transmitted by the TAS2770 to the master device as shown in Figure 41. With the exception of the last data byte, the master device responds with an acknowledge bit after receiving each data byte.

TAS2770 mbr_trn_los492.gif Figure 41. Multi-Byte Read Transfer

Register Organization

Device configuration and coefficients are stored using a page and book scheme. Each page contains 128 bytes and each book contains 256 pages. All device configuration registers are stored in book 0, page 0, which is the default setting at power up (and after a software reset). The book and page can be set by the BOOK[7:0] and PAGE[7:0] registers respectively.

Device Functional Modes

PDM Input

The TAS2770 provides one PDM input that can be used for low latency audio playback or sensor aggregation in TDM/I2C mode. Figure 42 below illustrates the double data rate nature of the PDM inputs. Each input has two interleaved PDM channels, one sampled by the rising edge and the other by the falling edge of the clock.

TAS2770 tas5770l_pdm_func.gif Figure 42. PDM Waveform

The PDM inputs are sampled by the PDMCK pin, which can be independently configured as either a PDM clock slave input or a PDM clock master output. The PDM_EDGE[1:0] and PDM_SLV[1:0] register bits select the sample clock edge and master/slave mode for each of the two PDM inputs. In master mode the PDMCK pin can disable the clocks (and drive a logic 0) by setting the PDM_GATE[1:0] register bits low. The PDM_CLK[1:0] register bits select which clock is used to sample each PDM input.

TAS2770 tas5770l_pdm_block_diagram.gif Figure 43. PDM Data and Clock Input Block Diagram

When configured as a clock slave, the PDM clock input does not require a specific phase relationship to the system clock (SBCLK in TDM/I2C Mode), but must have an exact frequency relationship to the audio sample rate. This is equivalent to 64/32/16 (~3 MHz) or 128/64/32 (~6 MHz) times a single/double/quadruple speed sample rate. The PDM rate is set by the PDM_RATE1[1:0] register bits.

When the PDMCK pin is configured as a clock master, the TAS2770 will output a 50% duty cycle clock of frequency that is set by the PDM_RATE1[1:0] register bits (64/32/16 or 128/64/32 times a single/double/quadruple speed sample rate).

The PDM_MAP register bit selects which PDM pin is used for audio playback input and which is used for PDM sensor input. The PDM sensor input can be decimated (time aligned with the IV sense) and transmitted on the SDOUT pin when the device is in TDM/I2C mode.

Table 3. PDM Input Capture Edge

PDM Input PinRegister BitValueCapture Edge
PDMDPDM_EDGE[1] 0Rising (default)
1Falling

Table 4. PDM Clock Slave

PDM Input PinRegister BitValueMaster/Slave
PDMDPDM_SLV[1] 0Slave (default)
1Master

Table 5. PDM Clock Select

PDM Input PinRegister BitValueClock Source
PDMDPDM_CLK[1] 0GND
1PDMCK (default)

Table 6. PDM Master Mode Clock Gate

PDM Clock PinRegister BitValueGating
PDMCKPDM_GATE[1] 0Gated Off (default)
1Active

Table 7. PDM Input Sample Rate

PDM Input PinRegister BitsValueSample Rate
PDMDPDM_RATE1[1:0] 002.54 - 3.38 MHz (default)
015.08 - 6.76 MHz
10Reserved
11Reserved

Table 8. PDM Pin Mapping

PDM_MAPMapping
0PDMD pin for sensor input (default)
1PDMD pin for playback

TDM Port

The TAS2770 provides a flexible TDM serial audio port for use in TDM/I2C Mode. The port can be configured to support a variety of formats including stereo I2S, Left Justified and TDM. Mono audio playback is available via the SDIN pin. The SDOUT pin is used to transmit sample streams including speaker voltage and current sense, VBAT voltage, die temperature and channel gain.

The TDM serial audio port supports up to 8 32-bit time slots at 44.1/48 kHz, 4 32-bit time slots at a 88.2/96 kHz sample rate and 2 32-bit time slots at a 176.4/192 kHz sample rate. The device supports 2 time slots at 32 bits in width and 4 or 8 time slots at 16, 24 or 32 bits in width. Valid SBCLK to FSYNC ratios are 64, 96, 128, 192, and 256.. Note that the device will automatically detect the number of time slots and this does not need to be programmed.

By default, the TAS2770 will automatically detect the PCM playback sample rate. This can be disabled by setting the AUTO_RATE register bit high.

The SAMP_RATE[2:0] register bits set the PCM audio sample rate when AUTO_RATE = 1. The TAS2770 employs a robust clock fault detection engine that will automatically volume ramp down the playback path if FSYNC does not match the configured sample rate (if AUTO_RATE = 1) or the ratio of SBCLK to FSYNC is not supported (minimizing any audible artifacts). Once the clocks are detected to be valid in both frequency and ratio, the device will automatically volume ramp the playback path back to the configured volume and resume playback.

Table 9. PCM Auto Sample Rate Detection

AUTO_RATESetting
0Enabled (default)
1Disabled

Table 10. PCM Audio Sample Rates

SAMP_RATE[1:0]Sample Rate
000Reserved
001Reserved
010Reserved
01144.1 kHz / 48 kHz (default)
10088.2 kHz / 96 kHz
101176.4 kHz / 192 kHz
110Reserved
111Reserved

Figure 44 and Figure 45 below illustrates the receiver frame parameters required to configure the port for playback. A frame begins with the transition of FSYNC from either high to low or low to high (set by the FRAME_START register bit). FSYNC and SDIN are sampled by SBCLK using either the rising or falling edge (set by the RX_EDGE register bit). The RX_OFFSET[4:0] register bits define the number of SBCLK cycles from the transition of FSYNC until the beginning of time slot 0. This is typically set to a value of 0 for Left Justified format and 1 for an I2S format.

TAS2770 tas5770l_tdm_rx1.gif Figure 44. TDM RX Time Slot with Left Justification
TAS2770 tas5770l_tdm_rx2.gif Figure 45. TDM RX Time Slots

Table 11. TDM Start of Frame Polarity

FRAME_STARTPolarity
0Low to High on FSYNC
1High to Low on FSYNC (default)

Table 12. TDM RX Capture Polarity

RX_EDGEFSYNC and SDIN Capture Edge
0Rising edge of SBCLK (default)
1Falling edge of SBCLK

Table 13. TDM RX Start of Frame to Time Slot 0 Offset

RX_OFFSET[4:0]SBCLK Cycles
0x000
0x011 (default)
0x022
......
0x1E30
0x1F31

The RX_SLEN[1:0] register bits set the length of the RX time slot. The length of the audio sample word within the time slot is configured by the RX_WLEN[1:0] register bits. The RX port will left justify the audio sample within the time slot by default, but this can be changed to right justification via the RX_JUSTIFY register bit. The TAS2770 supports mono and stereo down mix playback ([L+R]/2) via the left time slot, right time slot and time slot configuration register bits (RX_SLOT_L[3:0], RX_SLOT_R[3:0] and RX_SCFG[1:0] respectively). By default the device will playback mono from the time slot equal to the I2C base address offset (set by the MODE pin) for playback. The RX_SCFG[1:0] register bits can be used to override the playback source to the left time slot, right time slot or stereo down mix set by the RX_SLOT_L[3:0] and RX_SLOT_R[3:0] register bits.

If time slot selections places reception either partially or fully beyond the frame boundary, the receiver will return a null sample equivalent to a digitally muted sample.

Table 14. TDM RX Time Slot Length

RX_SLEN[1:0]Time Slot Length
0016-bits
0124-bits
1032-bits (default)
11reserved

Table 15. TDM RX Sample Word Length

RX_WLEN[1:0]Length
0016-bits
0120-bits
1024-bits (default)
1132-bits

Table 16. TDM RX Sample Justification

RX_JUSTIFYJustification
0Left (default)
1Right

Table 17. TDM RX Time Slot Select Configuration

RX_SCFG[1:0]Config Origin
00Mono with Time Slot equal to I2C Address Offset (default)
01Mono Left Channel
10Mono Right Channel
10Stereo Down Mix [L+R]/2

Table 18. TDM RX Left Channel Time Slot

RX_SLOT_L[3:0]Time Slot
0x00 (default)
0x11
......
0xE14
0xF15

Table 19. TDM RX Right Channel Time Slot

RX_SLOT_R[3:0]Time Slot
0x00 (default)
0x11
......
0xE14
0xF15

The TDM port can transmit a number sample streams on the SDOUT pin including speaker voltage sense, speaker current sense, decimated PDM input, VBAT voltage, die temperature and channel gain. Figure 46 below illustrates the alignment of time slots to the beginning of a frame and how a given sample stream is mapped to time slots. Either the rising or falling edge of SBCLK can be used to transmit data on the SDOUT pin, which can be configured by setting the TX_EDGE register bit. The TX_OFFSET[2:0] register bits define the number SBCLK cycles between the start of a frame and the beginning of time slot 0. This would typically be programmed to 0 for Left Justified format and 1 for I2S format. The TDM TX can either transmit logic 0 or Hi-Z depending on the setting of the TX_FILL register bit setting. An optional bus keeper will weakly hold the state of SDOUT when all devices driving are Hi-Z. Since only one bus keeper is required on SDOUT, this feature can be disabled via the TX_KEEPER register bit.

Each sample stream is composed of either one or two 8-bit time slots. Speaker voltage sense, speaker current sense and decimated PDM sample streams are 16-bit precision, so they will always utilize two TX time slots. The VBAT voltage stream is 12-bit precision, and can either be transmitted left justified in a 16-bit word (using two time slots) or can be truncated to 8-bits (the top 8 MSBs) and be transmitted in a single time slot. This is configured by setting VBAT_SLEN register bit. The Die temperature and gain are both 8-bit precision and are transmitted in a single time slot.

TAS2770 tas5770l_tdm_tx.gif Figure 46. TDM Port TX Diagram

Table 20. TDM TX Transmit Polarity

TX_EDGESDOUT Transmit Edge
0Rising edge of SBCLK
1Falling edge of SBCLK (default)

Table 21. TDM TX Start of Frame to Time Slot 0 Offset

TX_OFFSET[2:0]SBCLK Cycles
0x00
0x11 (default)
0x22
......
0x66
0x77

Table 22. TDM TX Unused Bit Field Fill

TX_FILLSDOUT Unused Bit Fields
0Transmit 0
1Transmit Hi-Z (default)

Table 23. TDM TX SDOUT Bus Keeper Enable

TX_KEEPERSDOUT Bus Keeper
0Disable bus keeper
1Enable bus keeper (default)

The time slot register for each sample stream defines where the MSB transmission begins. For instance, if VSNS_SLOT[5:0] is set to 2, the upper 8 MSBs will be transmitted in time slot 2 and the lower 8 LSBs will be transmitted in time slot 3. Each sample stream can be individually enabled or disabled. This is useful to manage limited TDM bandwidth since it may not be necessary to transmit all streams for all devices on the bus.

It is important to ensure that time slot assignments for actively transmitted sample streams do not conflict. For instance, if VSNS_SLOT[5:0] is set to 2 and ISNS_SLOT[5:0] is set to 3, the lower 8 LSBs of voltage sense will conflict with the upper 8 MSBs of current sense. This will produce unpredictable transmission results in the conflicting bit slots (i.e. the priority is not defined).

If time slot selections place transmission beyond the frame boundary, the transmitter will truncate transmission at the frame boundary.

Table 24. TDM Voltage Sense Time Slot

VSNS_SLOT[5:0]Slot
0x000 (default)
0x011
0x022
......
0x3E62
0x3F63

Table 25. TDM Voltage Sense Transmit Enable

VSNS_TXState
0Disabled (default)
1Enabled

Table 26. TDM Current Sense Time Slot

ISNS_SLOT[5:0]Slot
0x000
0x011
0x022 (default)
......
0x3E62
0x3F63

Table 27. TDM Current Sense Transmit Enable

ISNS_TXState
0Disabled (default)
1Enabled

Table 28. TDM Decimated PDM Input Time Slot

PDM_SLOT[5:0]Slot
0x000
0x011
......
0x044 (default)
......
0x3E62
0x3F63

Table 29. TDM Decimated PDM Input Transmit Enable

PDM_TXState
0Disabled (default)
1Enabled

Table 30. TDM VBAT Time Slot

VBAT_SLOT[5:0]Slot
0x000
0x011
......
0x066 (default)
......
0x3E62
0x3F63

Table 31. TDM VBAT Time Slot Length

VBAT_SLENSlot Length
0Truncate to 8-bits (default)
1Left justify to 16-bits

Table 32. TDM VBAT Transmit Enable

VBAT_TXState
0Disabled (default)
1Enabled

Table 33. TDM Temp Sensor Time Slot

TEMP_SLOT[5:0]Slot
0x000
0x011
......
0x077 (default)
......
0x3E62
0x3F63

Table 34. TDM Temp Sensor Transmit Enable

TEMP_TXState
0Disabled (default)
1Enabled

Table 35. TDM Limiter Gain Reduction Time Slot

GAIN_SLOT[5:0]Slot
0x000
0x011
......
0x088 (default)
......
0x3E62
0x3F63

Table 36. TDM Limiter Gain Reduction Transmit Enable

GAIN_TXState
0Disabled (default)
1Enabled

Playback Signal Path

High Pass Filter

Excessive DC and low frequency content in audio playback signal can damage loudspeakers, so the TAS2770 employs a high-pass filter (HPF) to prevent this from occurring for the PCM playback path. No HPF is available in the PDM playback path. Table 37 below shows the -3 dB corner frequencies available for each sample rate set by register bits HPF_FREQ[2:0]. The filter can be bypassed by setting the HPF_FREQ[2:0] register to 3'b000. The HPF Bi-Quad filter coefficients can also be directly programmed via the TBD register bits.

Table 37. HPF Filter Settings

HPF_FREQ[2:0]-3 dB FREQUENCY (Hz)
44.1/88.2/176.4 kHz 48/96/192 kHz
000 bypassbypass
001 1.8 (default)2 (default)
010 4650
011 92100
100 184200
101 368400
110 735800
111 ReservedReserved

Digital Volume Control and Amplifier Output Level

The gain from audio input to speaker terminals is controlled by setting the amplifier’s output level and digital volume control (DVC). A separate DVC is provided for PDM (available from the PDM input pins) and PCM (available from the TDM ports pins) playback paths.

Amplifier output level settings are presented in dBV (dB relative to 1 Vrms) with a full scale digital audio input (0 dBFS) and the digital volume control set to 0 dB. It should be noted that these levels may not be achievable because of analog clipping in the amplifier, so they should be used to convey gain only. Table 38 below shows analog gain settings that can be programmed via the AMP_LEVEL[4:0] register bits.

Table 38. Amplifier Output Level Settings

AMP_LEVEL[4:0]FULL SCALE OUTPUT
dBVVPEAK (V)
0x00 11.05.02
0x01 11.55.32
0x02 12.05.63
0x03 12.55.96
0x04 13.06.32
0x05 13.56.69
0x06 14.07.09
0x07 14.57.51
0x08 15.07.95
0x09 15.58.42
0x0A 16.08.92
0x0B 16.59.45
0x0C 17.010.0
0x0D 17.510.6
0x0E 18.011.2
0x0F 18.511.9
0x10 19.0 (default)12.6 (default)
0x11 19.513.4
0x12 20.014.1
0x13 20.514.98
0x14 21.015.87
0x15 - 0x1F ReservedReserved

Equation 1 calculates the amplifiers output voltage.

Equation 1. TAS2770 q_vamp_snos867.gif

where

  • VAMP is the amplifier output voltage in dBV
  • Input is the digital input amplitude in dB with respect to 0 dBFS
  • Advc is the digital volume control setting, 0 dB to -100 dB in 0.5 dB steps
  • AAMP is the amplifier output level setting in dBV

The digital volume control (DVC) is independently configurable for PCM and PDM streams from 0 dB to -100 dB in 0.5 dB steps by setting the DVC_PCM[7:0] and PVC_PDM[7:0] register bits respectively. Settings greater than 0xC8 are interpreted as mute. When a change in digital volume control occurs, the device ramps the volume to the new setting based on the DVC_RATE[1:0] register bits. If DVC_RATE[1:0] is set to 2'b11, volume ramping is disabled. This can be used to speed up startup, shutdown and digital volume changes when volume ramping is handled by the system master.

Table 39. PCM Digital Volume Control

DVC_PCM[7:0]Volume (dB)
0x000 (default)
0x01-0.5
0x02-1
......
0xC8-100
0xC9 - 0xFFMute

Table 40. PDM Digital Volume Control

DVC_PDM[7:0]Volume (dB)
0x000 (default)
0x01-0.5
0x02-1
......
0xC8-100
0xC9 - 0xFFMute

Table 41. Digital Volume Ramp Rate

DVC_RAMP[1:0]Ramp Rate
000.5 dB per 1 Sample (default)
010.5 dB per 4 Samples
100.5 dB per 8 Samples
11Volume Ramping Disabled

The Class-D amplifier uses a closed-loop architecture, so the gain does not depend on VBAT. The approximate threshold for the onset of analog clipping is calculated in Equation 2.

Equation 2. TAS2770 tas5770l_vpk_eq.gif

where

  • VPK(max,preclip) is the maximum peak unclipped output voltage in V
  • VBAT is the power supply voltage
  • RL is the speaker load in Ω
  • Rinterconnect is the additional resistance in the PCB (such as cabling and filters) in Ω
  • RFET(on) is the power stage total on resistance (HS FET+LS FET+Sense Resistor+bonding+packaging) in Ω

The effective on-resistance for this device (including HS+LS FET, Sense Resistor and bonding and packaging leads) is approximately 510 mΩ at room temperature. Table 42 shows approximate maximum unclipped peak output voltages at room temperature (excluding interconnect resistances).

Table 42. Approximate Maximum Unclipped Peak Output Voltage at Room Temperature

SUPPLY VOLTAGE
VBAT (V)
MAXIMUM UNCLIPPED
PEAK VOLTAGE
VPK (V)
RL = 4 ΩRL = 8 Ω
8.47.457.90
12.611.1811.84

Audio Playback Selection

Audio playback can be sourced from either PCM (via TDM) or PDM (via PDMD PDM Inputs) input sources via the PB_SRC register bit. The PB_PDM_SRC register bit determines the source of the PDM source.

Table 43. Audio Playback Source

PB_SRCSource
0PCM (default)
1PDM

Table 44. PDM Playback Source

PB_PDM_SRCSource
0PDM input pin defined by PDM_MAP register bit (default)
1Reserved

Battery Tracking Limiter with Brown Out Prevention

The TAS2770 monitors battery voltage (VBAT) and the audio signal to automatically decrease gain when the audio signal peaks exceed a programmable threshold. This helps prevent clipping and extends playback time through end of charge battery conditions. The limiter threshold can be configured to track VBAT below a programmable inflection point with a programmable slope. A minimum threshold sets the limit of threshold reduction from VBAT tracking. Configurable attack rate, hold time and release rate are provided to shape the dynamic response of the limiter (via LIM_ATK_RT[2:0], LIM_HLD_TM[2:0] and LIM_RLS_RT[2:0] register bits).

TAS2770 tas5770l_bop_lim.gif Figure 47. Limiter and Brown Out Prevention Interaction Diagram

A Brown Out Prevention (BOP) feature provides a priority input to the limiter to provide very fast response to transient dips in VBAT at end of charge conditions that can cause system level brown out. When VBAT dips below the BOP threshold, the limiter begins reducing gain with an attack latency of less than 10 µs and a configurable attack rate. When VBAT rises above the BOP threshold, the limiter will begin to release after the programmed hold time.

The limiter is enabled by setting the LIM_EN bit register bit high.

Table 45. Battery Tracking Limiter Enable

LIM_ENValue
0Disabled (default)
1Enabled

The limiter has configurable attack rate, hold time and release rate, which are available via the LIM_ATK_RT[2:0], LIM_HLD_TM[2:0] and LIM_RLS_RT[2:0] register bits respectively. The limiter attack and release step size can be set by configuring the LIM_ATK_ST[1:0] and LIM_RLS_ST[1:0] register bits respectively.

Table 46. Limiter Attack Rate

LIM_ATK_RT[2:0]Attack Rate (µs)
0x05
0x110
0x220 (default)
0x340
0x480
0x5160
0x6320
0x7640

Table 47. Limiter Hold Time

LIM_HLD_TM[2:0]Hold Time (ms)
0x00
0x110
0x225
0x350
0x4100
0x5250
0x6500 (default)
0x71000

Table 48. Limiter Release Rate

LIM_RLS_RT[2:0]Release Time (ms)
0x010
0x150
0x2100
0x3250
0x4500
0x5750
0x61000 (default)
0x71500

Table 49. Limiter Attack Step Size

LIM_ATK_ST[1:0]Step Size (dB)
000.25
010.5 (default)
101
112

Table 50. Limiter Release Step Size

LIM_RLS_ST[1:0]Step Size (dB)
000.25
010.5 (default)
101
112

A maximum level of attenuation applied by the limiter and brown out prevention feature is configurable via the LIM_MAX_ATN[4:0] register bits. This attenuation limit is shared between the features. For instance, if the maximum attenuation is set to 6 dB and the limiter has reduced gain by 4 dB, the brown out prevention feature will only be able to reduce the gain further by another 2 dB. If the limiter or brown out prevention feature is attacking and it reaches the maximum attenuation, gain will not be reduced any further.

Table 51. Limiter Max Attenuation

LIM_MAX_ATN[4:0]Attenuation (dB)
0x001
0x011.5
......
0x109 (default)
......
0x1E16
0x1F16.5

The limiter begins reducing gain when the output signal level is greater than the limiter threshold. The limiter can be configured to track VBAT below a programmable inflection point with a minimum threshold value. Figure 48 below shows the limiter configured to limit to a constant level regardless of VBAT level. To achieve this behavior, set the limiter maximum threshold to the desired level via the LIM_TH_MAX[6:0] register bits. Set the limiter inflection point (via the LIM_INF_PT[6:0] register bits) below the minimum allowable VBAT setting. The limiter minimum threshold register bits (LIM_TH_MIN[6:0]) do not impact limiter behavior in this use case.

TAS2770 tas5770l_limiter_fixed.gif Figure 48. Limiter with Fixed Threshold

Table 52. Limiter Maximum Threshold

LIM_TH_MAX[6:0]Threshold (V)
0x002
0x012.1
......
0x6E13 (default)
......
0x7E14.6
0x7F14.7

Table 53. Limiter Minimum Threshold

LIM_TH_MIN[6:0]Threshold (V)
0x002
0x012.1
......
0x1E5 (default)
......
0x7E14.6
0x7F14.7

Table 54. Limiter Inflection Point

LIM_INF_PT[6:0]Inflection Point (V)
0x002
0x012.1
......
0x5810.8 (default)
......
0x7E14.6
0x7F14.7

Figure 49 shows how to configure the limiter to track VBAT below a threshold without a minimum threshold. Set the LIM_TH_MAX[6:0] register bits to the desired threshold and LIM_INF_PT[6:0] register bits to the desired inflection point where the limiter will begin reducing the threshold with VBAT. The LIM_SLOPE[1:0] register bits can be used to change the slope of the limiter tracking with VBAT. The default value of 1 V/V will reduce the threshold 1 V for every 1 V of drop in VBAT. More aggressive tracking slopes can be programmed if desired. Program the LIM_TH_MIN[6:0] below the minimum VBAT to prevent the limiter from having a minimum threshold reduction when tracking VBAT.

TAS2770 tas5770l_limiter_inflection.gif Figure 49. Limiter with Inflection Point

Table 55. Limiter VBAT Tracking Slope

LIM_SLOPE[1:0]Slope (V/V)
001 (default)
011.5
102
114

To achieve a limiter that tracks VBAT below a threshold, configure the limiter as explained in the previous example, except program the LIM_TH_MIN[6:0] register bits to the desired minimum threshold. This is shown in Figure 50 below.

TAS2770 tas5770l_limiter_inf_min.gif Figure 50. Limiter with Inflection Point and Minimum Threshold

The TAS2770 also employs a Brown Out Prevention (BOP) feature that serves as a low latency priority input to the limiter engine that begins attacking within 10 µs of VBAT dipping below the programmed BOP threshold. This feature can be enabled by setting the BOP_EN register bit high. It should be noted that the BOP feature is independent of the limiter and will function if enabled even if the limiter is disabled. The BOP threshold is configured by setting the threshold with register bits BOP_TH[7:0].

TAS2770 tas5770l_limiter_block_diagram.gif Figure 51. Limiter Block Diagram

Table 56. Brown Out Prevention Enable

BOP_ENValue
0Disabled
1Enabled (default)

Table 57. Brown Out Prevention Threshold

BOP_TH[7:0]Threshold (V)
0x004.5
0x014.525
0x024.55
......
0x145.0 (default)
......
0xFE10.85
0xFF10.875

The BOP feature has a separate attack rate, attack step size and hold time from the battery tracking limiter (register bits BOP_ATK_RT[2:0], BOP_ATK_ST[1:0] and BOP_HLD_TM[2:0] respectively). The BOP feature uses the LIM_RLS_RT[2:0] register setting to release after a brown out event.

Table 58. Brown Out Prevention Attack Rate

BOP_ATK_RT[2:0]Attack Rate (µs)
0x05
0x110
0x220 (default)
0x340
0x480
0x5160
0x6320
0x7640

Table 59. Brown Out Prevention Attack Step Size

BOP_ATK_ST[1:0]Step Size (dB)
000.5
011 (default)
101.5
112

Table 60. Brown Out Prevention Hold Time

BOP_HLD_TM[2:0]Hold Time (ms)
0x00
0x110
0x225
0x350
0x4100
0x5250
0x6500 (default)
0x71000

The TAS2770 can also shutdown the device when a brown out event occurs if the BOP_SHUTDOWN register bit is set high. For the device to continue playing audio again, the device must transition through a SW/HW shutdown state. Setting the BOP_INF_HLD high will cause the limiter to stay in the hold state (i.e. never release) after a cleared brown out event until either the device transitions through a mute or SW/HW shutdown state or the register bit BOP_HLD_CLR is written to a high value (which will cause the device to exit the hold state and begin releasing). This bit is self clearing and will always readback low. Figure 52 below illustrates the entering and exiting from a brown out event.

TAS2770 tas5770l_limiter_bop_active.gif Figure 52. Brown Out Prevention Event

Table 61. Shutdown on Brown Out Event

BOP_SHUTDOWNValue
0Don't Shutdown (default)
1Shutdown

Table 62. Infinite Hold on Brown Out Event

BOP_INF_HLDValue
0Use BOP_HLD_TM after Brown Out event (default)
1Do not release until BOP_HLD_CLR is asserted high

Table 63. BOP Infinite Hold Clear

BOP_HLD_CLRValue
0Don't clear (default)
1Clear event (self clearing)

Inter Chip Limiter Alignment

TDM Mode

The TAS2770 supports alignment of limiter (including brown out prevention) dynamics across devices that share the same TDM bus. This ensures consistent gain between channels during limiting or brown out events since these dynamics are dependent on audio content, which can vary across channels. Each device can be configured to align to a specified number of other devices, which allows creation of groupings of devices that align only to each other.

Limiter activity is communicated via the limiter gain reduction parameter that can be optionally transmitted by each device on SDOUT in an 8-bit time slot. Gain reduction should be transmitted in adjacent time slots for all devices that are to be aligned beginning with the first slot that is specified by the ICLA_SLOT[5:0] register bits. The order of the devices is not important as long as they are adjacent. The time slot for limiter gain reduction is configured by the GAIN_SLOT[5:0] register bits and enabled by the GAIN_TX register bit.

The ICLA_SEN[7:0] register bits specify which time slots should be listened to for gain alignment. This allows any number of devices between two and eight to be grouped together. At least two of these bits should be enabled for alignment to take place. The ICLA_USE_MAX register bit determines whether alignment is based on the maximum or minimum gain reduction value from the group of enabled devices.

To enable the inter chip limiter alignment feature, the ICLA_EN register bit should be asserted high and all devices should be configured with identical limiter and brown out prevention settings. Limiter gain reduction transmission should be enabled on all devices as described above.

Table 64. Inter Chip Limiter Alignment

ICLA_ENValue
0Disabled (default)
1Enabled

Table 65. ICLA Alignment Configuration

ICLA_MODEValue
00Use the minimum gain reduction of the ICLA group including 0dB (default)
01Use the maximum gain reduction of the ICLA group
10Use the minimum gain reduction of the ICLA group that is non-0dB
11Reserved

Table 66. Inter Chip Limiter Alignment Starting Time Slot

ICLA_SLOT[5:0]Starting Time Slot
0x00Time Slot 0 (default)
0x01Time Slot 1
0x02Time Slot 2
......
0x3FTime Slot 63

Table 67. Inter Chip Limiter Alignment Time Slot Enable

Register BitDescriptionBit ValueState
ICLA_SEN[0]Time Slot = ICLA_SLOT[5:0]. When enabled, the limiter will include this time slot in the alignment group. 0Disabled (default)
1Enabled
ICLA_SEN[1]Time Slot = ICLA_SLOT[5:0] + 1. When enabled, the limiter will include this time slot in the alignment group. 0Disabled (default)
1Enabled
ICLA_SEN[2]Time Slot = ICLA_SLOT[5:0] + 2. When enabled, the limiter will include this time slot in the alignment group. 0Disabled (default)
1Enabled
ICLA_SEN[3]Time Slot = ICLA_SLOT[5:0] + 3. When enabled, the limiter will include this time slot in the alignment group. 0Disabled (default)
1Enabled
ICLA_SEN[4]Time Slot = ICLA_SLOT[5:0] + 4. When enabled, the limiter will include this time slot in the alignment group. 0Disabled (default)
1Enabled
ICLA_SEN[5]Time Slot = ICLA_SLOT[5:0] + 5. When enabled, the limiter will include this time slot in the alignment group. 0Disabled (default)
1Enabled
ICLA_SEN[6]Time Slot = ICLA_SLOT[5:0] + 6. When enabled, the limiter will include this time slot in the alignment group. 0Disabled (default)
1Enabled
ICLA_SEN[7]Time Slot = ICLA_SLOT[5:0] + 7. When enabled, the limiter will include this time slot in the alignment group. 0Disabled (default)
1Enabled

Class-D Settings

The TAS2770 Class-D amplifier supports spread spectrum PWM modulation, which can be enabled by setting the AMP_SS register bit high. This can help reduce EMI in some systems.

Table 68. Low EMI Spread Spectrum Mode

AMP_SSSpread Spectrum
0Disabled
1Enabled (default)

By default the Class-D amplifier's switching frequency is based on the device's trimmed internal oscillator. To synchronize switching to the audio sample rate, set the CLASSD_SYNC register bit high. When the Class-D is synchronized to the audio sample rate, the RATE_RAMP register bit must be set based whether the audio sample rate is based on a 44.1 kHz or 48 kHz frequency. For 44.1, 88.2 and 176.4 kHz, set this bit high. for 48, 96 and 192 kHz, set this bit low. This ensures that the internal ramp generator has the appropriate slope.

Table 69. Class-D Synchronization Mode

CLASSD_SYNCSynchronization Mode
0Not synchronized to audio clocks (default)
1Synchronized to audio clocks

Table 70. Sample Rate for Class-D Synchronized Mode

RAMP_RATEPlayback Sample Rate
048, 96 and 192 kHz (default)
144.1, 88.2 and 174.6 kHz

SAR ADC

A 12-bit SAR ADC monitors VBAT voltage and die temperature. The results of these conversions are available via register readback (VBAT_CNV[11:0] and TMP_CNV[7:0] registers respectively). VBAT voltage conversions are also used by the limiter and brown out prevention features.

The ADC runs at a fixed 667 kHz sample rate (1.5 µs per conversion) interleaved between VBAT voltage and die temperature measurements. This gives an effective sample rate of 333 kHz (3 µs per conversion) with a latency of 1 sample (1.5 µs). This gives a worst case measurement latency of 4.5 µs. Actual VBAT voltage is calculated by dividing the VBAT_CNV[11:0] register by 256. Actual die temperature is calculated by dividing the TMP_CNV[11:0] register by 16 and then subtracting 93.

Table 71. ADC VBAT Voltage Conversion

VBAT_CNV[11:0]VBAT Voltage (V)
0x0000 V
0x0010.0039 V
......
0xC9A 12.6016 V
......
0xFFE15.9922 V
0xFFF15.9961 V

Table 72. ADC Die Temperature Conversion

TMP_CNV[11:0]Die Temperature (°C)
0x000-93 °C
0x001-92.9375 °C
......
0x76025 °C
......
0xFFE162.8750 °C
0xFFF162.9375 °C

IV Sense

The TAS2770 provides speaker voltage and current sense for real time monitoring of loudspeaker behavior. The VSNS_P and VSNS_N pins should be connected after any ferrite bead filter (or directly to the OUT_P and OUT_N connections if no EMI filter is used). The V-Sense connections eliminate IR drop error due to packaging, PCB interconnect or ferrite bead filter resistance. It should be noted that any interconnect resistance after the V-Sense terminals will not be corrected for, so it is advised to connect the sense connections as close to the load as possible.

TAS2770 tas5770l_vsns_connect.gif Figure 53. V-Sense Connections

I-Sense and V-Sense can be powered down by asserting the ISNS_PD and VSNS_PD register bits respectively. When powered down, the device will return null samples for the powered down block.

Table 73. I-Sense Power Down

ISNS_PDSetting
0I-Sense is active (default)
1I-Sense is powered down

Table 74. V-Sense Power Down

VSNS_PDSetting
0V-Sense is active (default)
1V-Sense is powered down

Clocks and PLL

In TMD/I2C Mode, the device operates from SBCLK. Table 75 and Table 76 below shows the valid SBCLK frequencies for each sample rate and SBCLK to FSYNC ratio (for 44.1 kHz and 48 kHz family frequencies respectively.

If the sample rate is properly configured via the SAMP_RATE[1:0] bits, no additional configuration is required as long as the SBCLK to FSYNC ratio is valid. The device will detect improper SBCLK frequencies and SBCLK to FSYNC ratios and volume ramp down the playback path to minimize audible artifacts.

Table 75. Supported SBCLK Frequencies (48 kHz based sample rates)

Sample Rate (kHz)SBCLK to FSYNC Ratio
6496128192256384512
48 kHz3.072 MHz4.608 MHz6.144 MHz9.216 MHz12.288 MHz18.432 MHz24.576 MHz
96 kHz6.144 MHz9.216 MHz12.288 MHz18.432 MHz24.576 MHz - -
192 kHz12.288 MHz18.432 MHz24.576 MHz - - - -

Table 76. Supported SBCLK Frequencies (44.1 kHz based sample rates)

Sample Rate (kHz)SBCLK to FSYNC Ratio
6496128192256384512
44.1 kHz2.8224 MHz4.2336 MHz5.6448 MHz8.4672 MHz11.2896 MHz16.9344 MHz22.5792 MHz
88.2 kHz5.6448 MHz8.4672 MHz11.2896 MHz16.9344 MHz22.5792 MHz - -
176.4 kHz11.2896 MHz16.9344 MHz22.5792 MHz - - - -

Operational Modes

Hardware Shutdown

The device enters Hardware Shutdown mode if the SDZ pin is asserted low. In Hardware Shutdown mode, the device consumes the minimum quiescent current from AVDD and VBAT supplies. All registers loose state in this mode and communication is disabled (via I2C).

If SDZ is asserted low while audio is playing, the device will ramp down volume on the audio, stop the Class-D switching, power down analog and digital blocks and finally put the device into Hardware Shutdown mode.

When SDZ is released, the device will sample the MODE pin and enter the selected operational mode (i.e. either TDM/I2C).

Software Shutdown

Software Shutdown mode powers down all analog blocks required to playback audio, but does not cause the device to loose register state. Software Shutdown is enabled by asserting the MODE[1:0] register bits to 2'b10. If audio is playing when Software Shutdown is asserted, the Class-D will volume ramp down before shutting down. When deasserted, the Class-D will begin switching and volume ramp back to the programmed digital volume setting.

Mute

The TAS2770 will volume ramp down the Class-D amplifier to a mute state by setting the MODE[1:0] register bits to 2'b01. During mute the Class-D still switches, but transmits no audio content. If mute is deasserted, the device will volume ramp back to the programmed digital volume setting.

Active

In Active Mode the Class-D switches and plays back audio. Speaker voltage and current sensing are operational if enabled. PDM inputis also active if enabled. Set the MODE[1:0] register bits to 2'b00 to enter active mode.

Mode Control and Software Reset

The TAS2770 mode can be configured by writing the MODE[1:0] bits.

Table 77. Mode Control

MODE[1:0]Setting
00Active
01Mute
10Software Shutdown (default)
11Reserved

A software reset can be accomplished by asserting the SW_RESET bit, which is self clearing. This will restore all registers to their default values.

Table 78. Software Reset

SW_RESETSetting
0Don't reset (default)
1Reset

Faults and Status

During the power-up sequence, the power-on-reset circuit (POR) monitoring the AVDD pin will hold the device in reset (including all configuration registers) until the supply is valid. The device will not exit hardware shutdown until AVDD is valid and the SDZ pin is released. Once SDZ is released, the digital core voltage regulator will power up, enabling detection of the operational mode. If AVDD dips below the POR threshold, the device will immediately be forced into a reset state.

The device also monitors the VBAT supply and holds the analog core in power down if the supply is below the UVLO threshold or above the OVLO threshold. If the TAS2770 is in active operation and a UVLO or OVLO fault occurs, the analog supplies will immediately power down to protect the device. These faults are latching and require a transition through HW/SW shutdown to clear the fault. The live and latched registers will report UVLO/OVLO faults.

The device transitions into software shutdown mode if it detects any faults with the TDM clocks such as:

• Invalid SBCLK to FSYNC ratio

• Invalid FSYNC frequency

• Halting of SBCLK or FSYNC clocks

Upon detection of a TDM clock error, the device transitions into software shutdown mode as quickly as possible to limit the possibility of audio artifacts. Once all TDM clock errors are resolved, the device volume ramps back to its previous playback state. During a TDM clock error, the IRQZ pin will assert low if the clock error interrupt mask register bit is set low (INT_MASK[2]). The clock fault is also available for readback in the live or latched fault status registers (INT_LIVE[2] and INT_LTCH[2]). Reading the latched fault status register (INT_LTCH[7:0]) clears the register.

The TAS2770 also monitors die temperature and Class-D load current and will enter software shutdown mode if either of these exceed safe values. As with the TDM clock error, the IRQZ pin will assert low for these faults if the appropriate fault interrupt mask register bit is set low (INT_MASK[0] for over temp and INT_MASK[1] for over current). The fault status can also be monitored in the live and latched fault registers as with the TDM clock error.

Die over temp and Class-D over current errors can either be latching (i.e. the device will enter software shutdown until a HW/SW shutdown sequence is applied) or they can be configured to automatically retry after a prescribed time. This behavior can be configured in the OTE_RETRY and OCE_RETRY register bits (for over temp and over current respectively). Even in latched mode, the Class-D will not attempt to retry after an over temp or over current error until the retry time period (1.5s) has elapsed. This prevents applying repeated stress to the device in a rapid fashion that could lead to device damage. If the device has been cycled through SW/HW shutdown, the device will only begin to operate after the retry time period.

The status registers (and IRQZ pin if enabled via the status mask register) also indicates limiter behavior including when the limiter is activity, when VBAT is below the inflection point, when maximum attenuation has been applied, when the limiter is in infinite hold and when the limiter has muted the audio.

The IRQZ pin is an open drain output that asserts low during unmasked fault conditions and therefore must be pulled up with a resistor to IOVDD. An internal pull up resistor is provided in the TAS2770 and can be accessed by setting the IRQZ_PU register bit high. Figure 54 below highlights the IRQZ pin circuit.

TAS2770 tas5770l_faultz_circuit.gif Figure 54. IRQZ Pin

Table 79. Fault Interrupt Mask

INT_MASK[10:0] BitInterruptDefault (1 = Mask)
0Over Temp Error 0
1Over Current Error 0
2TDM Clock Error 1
3Limiter Active 1
4VBAT < Inf Point 1
5Limiter Max Atten 1
6Limiter Inf Hold 1
7Limiter Mute 1
8PDM Clock Error 1
9VBAT Brown Out 1
10VBAT UVLO 1
11VBAT OVLO 1

Table 80. IRQZ Internal Pull Up Enable

IRQZ_PUState
0Disabled (default)
1Enabled

Table 81. IRQZ Interrupt Configuration

IRQZ_PIN_CFG[1:0]Value
00IRQZ will assert on any unmasked live interrupts
01IRQZ will assert on any unmasked latched interrupts (default)
10Reserved
11Reserved

Power Sequencing Requirements

AVDD and IOVDD pins should be connected to the same 1.8 V supply domain. There are no other power sequencing requirements for order of rate of ramping up or down.

Digital Input Pull Downs

Each digital input and IO has an optional weak pull down to prevent the pin from floating. Pull downs are not enabled during HW shutdown.

Table 82. Digital Input Pull Down Enables

Register BitDescriptionBit ValueState
DIN_PD[0]Weak pull down for PDMCK. 0Disabled
1Enabled (default)
DIN_PD[2]Weak pull down for PDMD. 0Disabled
1Enabled (default)
DIN_PD[5]Weak pull down for FSYNC. 0Disabled
1Enabled (default)
DIN_PD[6]Weak pull down for SDIN. 0Disabled
1Enabled (default)
DIN_PD[7]Weak pull down for SDOUT. 0Disabled
1Enabled (default)

Register Maps

Register Summary Table Book=0x00 Page=0x00

AddrRegisterDescriptionSection
0x00PAGEDevice Page PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
0x01SW_RESETSoftware Reset SW_RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
0x02PWR_CTLPower Control PWR_CTL (book=0x00 page=0x00 address=0x02) [reset=Eh]
0x03PB_CFG0Playback Configuration 0 PB_CFG0 (book=0x00 page=0x00 address=0x03) [reset=10h]
0x04PB_CFG1Playback Configuration 1 PB_CFG1 (book=0x00 page=0x00 address=0x04) [reset=1h]
0x05PB_CFG2Playback Configuration 2 PB_CFG2 (book=0x00 page=0x00 address=0x05) [reset=0h]
0x06PB_CFG3Playback Configuration 3 PB_CFG3 (book=0x00 page=0x00 address=0x06) [reset=0h]
0x07MISC_CFGMisc Configuration MISC_CFG (book=0x00 page=0x00 address=0x07) [reset=6h]
0x08PDM_CFG0PDM Input Register 0 PDM_CFG0 (book=0x00 page=0x00 address=0x08) [reset=0h]
0x09PDM_CFG1PDM Configuration 1 PDM_CFG1 (book=0x00 page=0x00 address=0x09) [reset=8h]
0x0ATDM_CFG0TDM Configuration 0 TDM_CFG0 (book=0x00 page=0x00 address=0x0A) [reset=7h]
0x0BTDM_CFG1TDM Configuration 1 TDM_CFG1 (book=0x00 page=0x00 address=0x0B) [reset=2h]
0x0CTDM_CFG2TDM Configuration 2 TDM_CFG2 (book=0x00 page=0x00 address=0x0C) [reset=Ah]
0x0DTDM_CFG3TDM Configuration 3 TDM_CFG3 (book=0x00 page=0x00 address=0x0D) [reset=10h]
0x0ETDM_CFG4TDM Configuration 4 TDM_CFG4 (book=0x00 page=0x00 address=0x0E) [reset=13h]
0x0FTDM_CFG5TDM Configuration 5 TDM_CFG5 (book=0x00 page=0x00 address=0x0F) [reset=2h]
0x10TDM_CFG6TDM Configuration 6 TDM_CFG6 (book=0x00 page=0x00 address=0x10) [reset=0h]
0x11TDM_CFG7TDM Configuration 7 TDM_CFG7 (book=0x00 page=0x00 address=0x11) [reset=4h]
0x12TDM_CFG8TDM Configuration 8 TDM_CFG8 (book=0x00 page=0x00 address=0x12) [reset=6h]
0x13TDM_CFG9TDM Configuration 9 TDM_CFG9 (book=0x00 page=0x00 address=0x13) [reset=7h]
0x14TDM_CFG10TDM Configuration 10 TDM_CFG10 (book=0x00 page=0x00 address=0x14) [reset=8h]
0x15LIM_CFG0Limiter Configuration 0 LIM_CFG0 (book=0x00 page=0x00 address=0x15) [reset=14h]
0x16LIM_CFG1Limiter Configuration 1 LIM_CFG1 (book=0x00 page=0x00 address=0x16) [reset=76h]
0x17LIM_CFG2Limiter Configuration 2 LIM_CFG2 (book=0x00 page=0x00 address=0x17) [reset=10h]
0x18LIM_CFG3Limiter Configuration 3 LIM_CFG3 (book=0x00 page=0x00 address=0x18) [reset=6Eh]
0x19LIM_CFG4Limiter Configuration 4 LIM_CFG4 (book=0x00 page=0x00 address=0x19) [reset=1Eh]
0x1ALIM_CFG5Limiter Configuration 5 LIM_CFG5 (book=0x00 page=0x00 address=0x1A) [reset=58h]
0x1BBOP_CFG0Brown Out Prevention 0 BOP_CFG0 (book=0x00 page=0x00 address=0x1B) [reset=1h]
0x1CBOP_CFG1Brown Out Prevention 1 BOP_CFG1 (book=0x00 page=0x00 address=0x1C) [reset=14h]
0x1DBOP_CFG2Brown Out Prevention 2 BOP_CFG2 (book=0x00 page=0x00 address=0x1D) [reset=4Eh]
0x1EICLA_CFG0Inter Chip Limiter Alignment 0 ICLA_CFG0 (book=0x00 page=0x00 address=0x1E) [reset=0h]
0x1FICLA_CFG1Inter Chip Limiter Alignment 1 ICLA_CFG1 (book=0x00 page=0x00 address=0x1F) [reset=0h]
0x20INT_MASK0Interrupt Mask 0 INT_MASK0 (book=0x00 page=0x00 address=0x20) [reset=FCh]
0x21INT_MASK1Interrupt Mask 1 INT_MASK1 (book=0x00 page=0x00 address=0x21) [reset=B1h]
0x22INT_LIVE0Live Interrupt Readback 0 INT_LIVE0 (book=0x00 page=0x00 address=0x22) [reset=0h]
0x23INT_LIVE1Live Interrupt Readback 1 INT_LIVE1 (book=0x00 page=0x00 address=0x23) [reset=0h]
0x24INT_LTCH0Latched Interrupt Readback 0 INT_LTCH0 (book=0x00 page=0x00 address=0x24) [reset=0h]
0x25INT_LTCH1Latched Interrupt Readback 1 INT_LTCH1 (book=0x00 page=0x00 address=0x25) [reset=0h]
0x27VBAT_MSBSAR ADC Conversion 0 VBAT_MSB (book=0x00 page=0x00 address=0x27) [reset=0h]
0x28VBAT_LSBSAR ADC Conversion 1 VBAT_LSB (book=0x00 page=0x00 address=0x28) [reset=0h]
0x29TEMP_MSBSAR ADC Conversion 2 TEMP_MSB (book=0x00 page=0x00 address=0x29) [reset=0h]
0x2ATEMP_LSBSAR ADC Conversion 2 TEMP_LSB (book=0x00 page=0x00 address=0x2A) [reset=0h]
0x30INT_CFGInterrupt Configuration INT_CFG (book=0x00 page=0x00 address=0x30) [reset=5h]
0x31DIN_PDDigital Input Pin Pull Down DIN_PD (book=0x00 page=0x00 address=0x31) [reset=0h]
0x32MISC_IRQMisc Configuration MISC_IRQ (book=0x00 page=0x00 address=0x32) [reset=81h]
0x3CCLOCK_CFGClock Configuration CLOCK_CFG (book=0x00 page=0x00 address=0x3C) [reset=Dh]
0x77TDM_DETTDM Clock detection monitor TDM_DET (book=0x00 page=0x00 address=0x77) [reset=7Fh]
0x7DREV_IDRevision and PG ID REV_ID (book=0x00 page=0x00 address=0x7D) [reset=20h]
0x7EI2C_CKSUMI2C Checksum I2C_CKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]
0x7FBOOKDevice Book BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]

Register Maps

PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]

The device's memory map is divided into pages and books. This register sets the page.

Figure 55. PAGE Register Address: 0x00
76543210
PAGE[7:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 83. Device Page Field Descriptions

BitFieldTypeResetDescription
7-0PAGE[7:0]RW0hSets the device page.
00h = Page 0

01h = Page 1

...

FFh = Page 255

SW_RESET (book=0x00 page=0x00 address=0x01) [reset=0h]

Asserting Software Reset will place all register values in their default POR (Power on Reset) state.

Figure 56. SW_RESET Register Address: 0x01
76543210
ReservedSW_RESET
RW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 84. Software Reset Field Descriptions

BitFieldTypeResetDescription
7-1ReservedRW0hReserved
0SW_RESETRW0hSoftware reset. Bit is self clearing.
0b = Don't reset

1b = Reset

PWR_CTL (book=0x00 page=0x00 address=0x02) [reset=Eh]

Sets device's mode of operation and power down of IV sense blocks.

Figure 57. PWR_CTL Register Address: 0x02
76543210
ReservedReservedReservedISNS_PDVSNS_PDMODE[1:0]
RW-0hRW-0hRW-0hRW-1hRW-1hRW-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 85. Power Control Field Descriptions

BitFieldTypeResetDescription
7-6ReservedRW0hReserved
5ReservedRW0hReserved
4ReservedRW0hReserved
3ISNS_PDRW1hCurrent sense power down.
0b = Current sense active

1b = Current sense is powered down
2VSNS_PDRW1hVoltage sense power down.
0b = voltage sense is active

1b = Voltage sense is powered down
1-0MODE[1:0]RW2hDevice operational mode.
00b = Active

01b = Mute

10b = Software Shutdown

11b = Reserved

PB_CFG0 (book=0x00 page=0x00 address=0x03) [reset=10h]

Sets playback source, including PDM input and amplifier output level setting.

Figure 58. PB_CFG0 Register Address: 0x03
76543210
PDM_MAPPB_PDM_SRCPB_SRCAMP_LEVEL[4:0]
RW-0hRW-0hRW-0hRW-10h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 86. Playback Configuration 0 Field Descriptions

BitFieldTypeResetDescription
7PDM_MAPRW0hPDM Pin Mapping
0b = PDMD1 for sensor input.

1b = PDMD1 for playback.
6PB_PDM_SRCRW0hPDM playback source.
0b = PDM input pin defined by PDM_MAP.

1b = Reserved.
5PB_SRCRW0hPlayback source.
0b = PCM

1b = PDM
4-0AMP_LEVEL[4:0]RW10hAmplifier output level setting.
00h = 11.0 dBV (5.02 Vpk)

01h = 11.5 dBV (5.32 Vpk)

02h = 12.0 dBV (5.63 Vpk)

03h = 12.5 dBV (5.96 Vpk)

04h = 13.0 dBV (6.32 Vpk)

05h = 13.5 dBV (6.69 Vpk)

06h = 14.0 dBV (7.09 Vpk)

07h = 14.5 dBV (7.51 Vpk)

08h = 15.0 dBV (7.95 Vpk)

09h = 15.5 dBV (8.42 Vpk)

0Ah = 16.0 dBV (8.92 Vpk)

0Bh = 16.5 dBV (9.45 Vpk)

0Ch = 17.0 dBV (10.01 Vpk)

0Dh = 17.5 dBV (10.61 Vpk)

0Eh = 18.0 dBV (11.23 Vpk)

0Fh = 18.5 dBV (11.90 Vpk)

10h = 19.0 dBV (12.60 Vpk)

11h = 19.5 dBV (13.35 Vpk)

12h = 20.0 dBV (14.14 Vpk)

13h = 20.5 dBV (14.98 Vpk)

14h = 21.0 dBV (15.87 Vpk)

15h - 1Fh = Reserved

PB_CFG1 (book=0x00 page=0x00 address=0x04) [reset=1h]

Sets playback high pass filter corner (PCM playback only).

Figure 59. PB_CFG1 Register Address: 0x04
76543210
ReservedReservedReservedReservedReservedHPF_FREQ[2:0]
RW-0hRW-0hRW-0hRW-0hRW-0hRW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 87. Playback Configuration 1 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6ReservedRW0hReserved
5ReservedRW0hReserved
4ReservedRW0hReserved
3ReservedRW0hReserved
2-0HPF_FREQ[2:0]RW1hHigh Pass Filter Corner Frequency.
000b = Bypass

001b = 2 Hz

010b = 50 Hz

011b = 100 Hz

100b = 200 Hz

101b = 400 Hz

110b = 800 Hz

111b = Reserved

PB_CFG2 (book=0x00 page=0x00 address=0x05) [reset=0h]

Sets playback volume for PCM playback path.

Figure 60. PB_CFG2 Register Address: 0x05
76543210
DVC_PCM[7:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 88. Playback Configuration 2 Field Descriptions

BitFieldTypeResetDescription
7-0DVC_PCM[7:0]RW0hPCM digital volume control.
00h = 0 dB

01h = -0.5 dB

02h = -1 dB

....

C7h = -99.5 dB

C8h = -100dB

C9h - FFh = Mute

PB_CFG3 (book=0x00 page=0x00 address=0x06) [reset=0h]

Sets playback volume for PDM playback path.

Figure 61. PB_CFG3 Register Address: 0x06
76543210
DVC_PDM[7:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 89. Playback Configuration 3 Field Descriptions

BitFieldTypeResetDescription
7-0DVC_PDM[7:0]RW0hPDM digital volume control.
00h = 0 dB

01h = -0.5 dB

02h = -1 dB

....

C7h = -99.5 dB

C8h = -100dB

C9h - FFh = Mute

MISC_CFG (book=0x00 page=0x00 address=0x07) [reset=6h]

Sets DVC Ramp Rate, IRQZ pull up, amp spread spectrum and I-Sense current range.

Figure 62. MISC_CFG Register Address: 0x07
76543210
DVC_RAMP_RATE[1:0]ReservedIRQZ_PUAMP_SSReserved
RW-0hRW-0hRW-0hRW-1hRW-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 90. Misc Configuration Field Descriptions

BitFieldTypeResetDescription
7-6DVC_RAMP_RATE[1:0]RW0hDigital volume control ramp rate.
00b = 0.5 dB per 1 sample

01b = 0.5 dB per 4 samples

10b = 0.5 dB per 8 samples

11b = Volume ramping disabled
5-4ReservedRW0hReserved
3IRQZ_PURW0hIRQZ internal pull up enable.
0b = Disabled

1b = Enabled
2AMP_SSRW1hLow EMI spread spectrum enable.
0b = Disabled

1b = Enabled
1-0ReservedRW2hReserved

PDM_CFG0 (book=0x00 page=0x00 address=0x08) [reset=0h]

Sets Class-D sync mode and PDM sample rates.

Figure 63. PDM_CFG0 Register Address: 0x08
76543210
ReservedCLASSD_SYNCReservedPDM_RATE1[1:0]Reserved
RW-0hRW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 91. PDM Input Register 0 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6CLASSD_SYNCRW0hClass-D synchronization mode.
0b = Not synchronized to audio clocks

1b = Synchronized to audio clocks
5-4ReservedRW0hReserved
3-2PDM_RATE1[1:0]RW0hPDMD1 input sample rate.
00b = 2.54 - 3.38 MHz

01b = 5.08 - 6.76 MHz

10b = Reserved

11b = Reserved
1-0ReservedRW0hReserved

PDM_CFG1 (book=0x00 page=0x00 address=0x09) [reset=8h]

Sets PDM capture edge, master/slave, clock source and gating.

Figure 64. PDM_CFG1 Register Address: 0x09
76543210
PDM_EDGE1ReservedPDM_SLV1ReservedPDM_CLK1ReservedPDM_GATE1Reserved
RW-0hRW-0hRW-0hRW-0hRW-1hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 92. PDM Configuration 1 Field Descriptions

BitFieldTypeResetDescription
7PDM_EDGE1RW0hPDMD1 input capture edge.
0b = Rising
1b = Falling
6ReservedRW0hReserved
5PDM_SLV1RW0hPDMD1 input master or slave.
0b = Slave
1b = Master
4ReservedRW0hReserved
3PDM_CLK1RW1hPDMD1 clock select.
0b = GND
1b = PDMCK1
2ReservedRW0hReserved
1PDM_GATE1RW0hPDMD1 clock gate.
0b = Gated Off
1b = Active
0ReservedRW0hReserved

TDM_CFG0 (book=0x00 page=0x00 address=0x0A) [reset=7h]

Sets the TDM frame start, TDM sample rate, TDM auto rate detection and whether rate is based on 44.1 kHz or 48 kHz frequency.

Figure 65. TDM_CFG0 Register Address: 0x0A
76543210
ReservedRATE_RAMPAUTO_RATESAMP_RATE[2:0]FRAME_START
RW-0hRW-0hRW-0hRW-3hRW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 93. TDM Configuration 0 Field Descriptions

BitFieldTypeResetDescription
7-6ReservedRW0hReserved
5RATE_RAMPRW0hSample rate based on 44.1kHz or 48kHz when CLASSD_SYNC=1.
0b = 48kHz

1b = 44.1kHz
4AUTO_RATERW0hAuto detection of TDM sample rate.
0b = Enabled

1b = Disabled
3-1SAMP_RATE[2:0]RW3hSample rate of the TDM bus.
000b = Reserved

001b = Reserved

010b = Reserved

011b = 44.1/48 kHz

100b = 88.2/96 kHz

101b = 176.4/192 kHz

110b = Reserved

111b = Reserved
0FRAME_STARTRW1hTDM frame start polarity.
0b = Low to High on FSYNC

1b = High to Low on FSYNC

TDM_CFG1 (book=0x00 page=0x00 address=0x0B) [reset=2h]

Sets TDM RX justification, offset and capture edge.

Figure 66. TDM_CFG1 Register Address: 0x0B
76543210
ReservedRX_JUSTIFYRX_OFFSET[4:0]RX_EDGE
RW-0hRW-0hRW-1hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 94. TDM Configuration 1 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6RX_JUSTIFYRW0hTDM RX sample justification within the time slot.
0b = Left

1b = Right
5-1RX_OFFSET[4:0]RW1hTDM RX start of frame to time slot 0 offset (SBCLK cycles).
0RX_EDGERW0hTDM RX capture clock polarity.
0b = Rising edge of SBCLK

1b = Falling edge of SBCLK

TDM_CFG2 (book=0x00 page=0x00 address=0x0C) [reset=Ah]

Sets TDM RX time slot select, word length and time slot length.

Figure 67. TDM_CFG2 Register Address: 0x0C
76543210
ReservedRX_SCFG[1:0]RX_WLEN[1:0]RX_SLEN[1:0]
RW-0hRW-0hRW-2hRW-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 95. TDM Configuration 2 Field Descriptions

BitFieldTypeResetDescription
7-6ReservedRW0hReserved
5-4RX_SCFG[1:0]RW0hTDM RX time slot select config.
00b = Mono with time slot equal to I2C address offset

01b = Mono left channel

10b = Mono right channel

11b = Stereo downmix (L+R)/2
3-2RX_WLEN[1:0]RW2hTDM RX word length.
00b = 16-bits

01b = 20-bits

10b = 24-bits

11b = 32-bits
1-0RX_SLEN[1:0]RW2hTDM RX time slot length.
00b = 16-bits

01b = 24-bits

10b = 32-bits

11b = Reserved

TDM_CFG3 (book=0x00 page=0x00 address=0x0D) [reset=10h]

Sets TDM RX left and right time slots.

Figure 68. TDM_CFG3 Register Address: 0x0D
76543210
RX_SLOT_R[3:0]RX_SLOT_L[3:0]
RW-1hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 96. TDM Configuration 3 Field Descriptions

BitFieldTypeResetDescription
7-4RX_SLOT_R[3:0]RW1hTDM RX Right Channel Time Slot.
3-0RX_SLOT_L[3:0]RW0hTDM RX Left Channel Time Slot.

TDM_CFG4 (book=0x00 page=0x00 address=0x0E) [reset=13h]

Sets TDM TX bus keeper, fill, offset and transmit edge.

Figure 69. TDM_CFG4 Register Address: 0x0E
76543210
TX_LSB_CFGTX_KEEPER_CFGTX_KEEPERTX_FILLTX_OFFSET[2:0]TX_EDGE
RW-0hRW-0hRW-0hRW-1hRW-1hRW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 97. TDM Configuration 4 Field Descriptions

BitFieldTypeResetDescription
7TX_LSB_CFGRW0hTDM TX SDOUT LSB data option
0b = TX SDOUT LSB is driven for full-cycle (provided TX_KEEPER is '0')
1b = TX SDOUT LSB is driven for half-cycle
6TX_KEEPER_CFGRW0hTDM TX SDOUT bus keeper configuration.
0b = Bus keeper is enabled only for 1 LSB bit cycle & SDOUT LSB driven for half cycle (provided TX_KEEPER is '1')
1b = Bus keeper is always enabled & SDOUT LSB driven for half cycle (provided TX_KEEPER is '1')
5TX_KEEPERRW0hTDM TX SDOUT bus keeper enable.
0b = Disable bus keeper

1b = Enable bus keeper
4TX_FILLRW1hTDM TX SDOUT unused bitfield fill.
0b = Transmit 0

1b = Transmit Hi-Z
3-1TX_OFFSET[2:0]RW1hTDM TX start of frame to time slot 0 offset.
0TX_EDGERW1hTDM TX launch clock polarity.
0b = Rising edge of SBCLK

1b = Falling edge of SBCLK

TDM_CFG5 (book=0x00 page=0x00 address=0x0F) [reset=2h]

Sets TDM TX V-Sense time slot and enable.

Figure 70. TDM_CFG5 Register Address: 0x0F
76543210
ReservedVSNS_TXVSNS_SLOT[5:0]
RW-0hRW-0hRW-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 98. TDM Configuration 5 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6VSNS_TXRW0hTDM TX voltage sense transmit enable.
0b = Disabled

1b = Enabled
5-0VSNS_SLOT[5:0]RW2hTDM TX voltage sense time slot. It is recommended to maintain the following order: ISNS_SLOT<VSNS_SLOT<PDM_SLOT<VBAT_SLOT<TEMP_SLOT<GAIN_SLOT

TDM_CFG6 (book=0x00 page=0x00 address=0x10) [reset=0h]

Sets TDM TX I-Sense time slot and enable.

Figure 71. TDM_CFG6 Register Address: 0x10
76543210
ReservedISNS_TXISNS_SLOT[5:0]
RW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 99. TDM Configuration 6 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6ISNS_TXRW0hTDM TX current sense transmit enable.
0b = Disabled

1b = Enabled
5-0ISNS_SLOT[5:0]RW0hTDM TX current sense time slot. It is recommended to maintain the following order: ISNS_SLOT<VSNS_SLOT<PDM_SLOT<VBAT_SLOT<TEMP_SLOT<GAIN_SLOT

TDM_CFG7 (book=0x00 page=0x00 address=0x11) [reset=4h]

Sets TDM TX time slot and transmit enable for decimated PDM.

Figure 72. TDM_CFG7 Register Address: 0x11
76543210
ReservedPDM_TXPDM_SLOT[5:0]
RW-0hRW-0hRW-4h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 100. TDM Configuration 7 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6PDM_TXRW0hTDM TX decimated PDM transmit enable.
0b = Disabled

1b = Enabled
5-0PDM_SLOT[5:0]RW4hTDM TX decimated PDM time slot.

TDM_CFG8 (book=0x00 page=0x00 address=0x12) [reset=6h]

Sets TDM TX VBAT time slot and enable.

Figure 73. TDM_CFG8 Register Address: 0x12
76543210
VBAT_SLENVBAT_TXVBAT_SLOT[5:0]
RW-0hRW-0hRW-6h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 101. TDM Configuration 8 Field Descriptions

BitFieldTypeResetDescription
7VBAT_SLENRW0hTDM TX VBAT time slot length.
0b = Truncate to 8-bits

1b = Left justify to 16-bits
6VBAT_TXRW0hTDM TX VBAT transmit enable.
0b = Disabled

1b = Enabled
5-0VBAT_SLOT[5:0]RW6hTDM TX VBAT time slot.

TDM_CFG9 (book=0x00 page=0x00 address=0x13) [reset=7h]

Sets TDM TX temp time slot and enable.

Figure 74. TDM_CFG9 Register Address: 0x13
76543210
ReservedTEMP_TXTEMP_SLOT[5:0]
RW-0hRW-0hRW-7h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 102. TDM Configuration 9 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6TEMP_TXRW0hTDM TX temp sensor transmit enable.
0b = Disabled

1b = Enabled
5-0TEMP_SLOT[5:0]RW7hTDM TX temp sensor time slot.

TDM_CFG10 (book=0x00 page=0x00 address=0x14) [reset=8h]

Sets TDM TX limiter gain reduction time slot and enable.

Figure 75. TDM_CFG10 Register Address: 0x14
76543210
ReservedGAIN_TXGAIN_SLOT[5:0]
RW-0hRW-0hRW-8h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 103. TDM Configuration 10 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6GAIN_TXRW0hTDM TX limiter gain reduction transmit enable.
0b = Disabled

1b = Enabled
5-0GAIN_SLOT[5:0]RW8hTDM TX limiter gain reduction time slot.

LIM_CFG0 (book=0x00 page=0x00 address=0x15) [reset=14h]

Sets Limiter attack step size, attack rate and enable.

Figure 76. LIM_CFG0 Register Address: 0x15
76543210
ReservedLIM_ATK_ST[1:0]LIM_ATK_RT[2:0]LIM_EN
RW-0hRW-1hRW-2hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 104. Limiter Configuration 0 Field Descriptions

BitFieldTypeResetDescription
7-6ReservedRW0hReserved
5-4LIM_ATK_ST[1:0]RW1hLimiter/ICLA attack step size.
00b = 0.25 dB

01b = 0.5 dB

10b = 1 dB

11b = 2 dB
3-1LIM_ATK_RT[2:0]RW2hLimiter/ICLA attack rate.
000b = 5 us/step

001b = 10 us/step

010b = 20 us/step

011b = 40 us/step

100b = 80 us/step

101b = 160 us/step

110b = 320 us/step

111b = 640 us/step
0LIM_ENRW0hLimiter enable.
0b = Disabled

1b = Enabled

LIM_CFG1 (book=0x00 page=0x00 address=0x16) [reset=76h]

Sets limiter release step size, release rate and hold time.

Figure 77. LIM_CFG1 Register Address: 0x16
76543210
LIM_RLS_ST[1:0]LIM_RLS_RT[2:0]LIM_HLD_TM[2:0]
RW-1hRW-6hRW-6h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 105. Limiter Configuration 1 Field Descriptions

BitFieldTypeResetDescription
7-6LIM_RLS_ST[1:0]RW1hLimiter/BOP/ICLA release step size.
00b = 0.25 dB

01b = 0.5 dB

10b = 1 dB

11b = 2 dB
5-3LIM_RLS_RT[2:0]RW6hLimiter/BOP/ICLA release rate.
000b = 10 ms/step

001b = 50 ms/step

010b = 100 ms/step

011b = 250 ms/step

100b = 500 ms/step

101b = 750 ms/step

110b = 1000 ms/step

111b = 1500 ms/step
2-0LIM_HLD_TM[2:0]RW6hLimiter hold time.
000b = 0 ms

001b = 10 ms

010b = 25 ms

011b = 50 ms

100b = 100 ms

101b = 250 ms

110b = 500 ms

111b = 1000 ms

LIM_CFG2 (book=0x00 page=0x00 address=0x17) [reset=10h]

Sets limiter VBAT tracking slope and max attenuatio.

Figure 78. LIM_CFG2 Register Address: 0x17
76543210
ReservedLIM_MAX_ATN[4:0]
RW-0hRW-10h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 106. Limiter Configuration 2 Field Descriptions

BitFieldTypeResetDescription
7-5ReservedRW0hReserved
4-0LIM_MAX_ATN[4:0]RW10hLimiter max attenuation.
00h = 1 dB

01h = 1.5 dB

...

10h = 9 dB

...

1Eh = 16 dB

1Fh = 16.5 dB

LIM_CFG3 (book=0x00 page=0x00 address=0x18) [reset=6Eh]

Sets Limiter max threshold.

Figure 79. LIM_CFG3 Register Address: 0x18
76543210
ReservedLIM_TH_MAX[6:0]
RW-0hRW-6Eh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 107. Limiter Configuration 3 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-0LIM_TH_MAX[6:0]RW6EhLimiter max threshold.
00h = 2 V

01h = 2.1 V

...

6Eh = 13 V

...

7Eh = 14.6 V

7Fh = 14.7 V

LIM_CFG4 (book=0x00 page=0x00 address=0x19) [reset=1Eh]

Sets limiter min threshold.

Figure 80. LIM_CFG4 Register Address: 0x19
76543210
ReservedLIM_TH_MIN[6:0]
RW-0hRW-1Eh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 108. Limiter Configuration 4 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-0LIM_TH_MIN[6:0]RW1EhLimiter min threshold.
00h = 2 V

01h = 2.1 V

...

1Eh = 5 V

...

7Eh = 14.6 V

7Fh = 14.7 V

LIM_CFG5 (book=0x00 page=0x00 address=0x1A) [reset=58h]

Sets limiter inflection point.

Figure 81. LIM_CFG5 Register Address: 0x1A
76543210
ReservedLIM_INF_PT[6:0]
RW-0hRW-58h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 109. Limiter Configuration 5 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-0LIM_INF_PT[6:0]RW58hLimiter inflection point.
00h = 2 V

01h = 2.1 V

...

58h = 10.8 V

...

7Eh = 14.6 V

7Fh = 14.7 V

BOP_CFG0 (book=0x00 page=0x00 address=0x1B) [reset=1h]

Sets BOP infinite hold clear, infinite hold enable, mute on brown out and enable.

Figure 82. BOP_CFG0 Register Address: 0x1B
76543210
ReservedEN_BO_RECOVERY_HYSTERSISLIM_SLOPE[1:0]BOP_HLD_CLRBOP_INF_HLDBOP_MUTEBOP_EN
RW-0hRW-0hRW-0hRW-0hRW-0hRW-0hRW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 110. Brown Out Prevention 0 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6EN_BO_RECOVERY_HYSTERSISRW0h
5-4LIM_SLOPE[1:0]RW0hLimiter VBAT tracking slope.
00b = 1 V/V

01b = 1.5 V/V

10b = 2 V/V

11b = 4 V/V
3BOP_HLD_CLRRW0hBOP infinite hold clear (self clearing).
0b = Don't clear

1b = Clear
2BOP_INF_HLDRW0hInfinite hold on brown out event.
0b = Use BOP_HLD_TM after brown out event

1b = Don't release until BOP_HLD_CLR is asserted high
1BOP_MUTERW0hMute on brown out event.
0b = Don't mute

1b = Mute followed by device shutdown
0BOP_ENRW1hBrown out prevention enable.
0b = Disabled

1b = Enabled

BOP_CFG1 (book=0x00 page=0x00 address=0x1C) [reset=14h]

BOP threshold.

Figure 83. BOP_CFG1 Register Address: 0x1C
76543210
BOP_TH[7:0]
RW-14h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 111. Brown Out Prevention 1 Field Descriptions

BitFieldTypeResetDescription
7-0BOP_TH[7:0]RW14hBrown out prevention threshold.
00h = 4.5 V

01h = 4.525 V

...

14h = 5.0 V

...

FEh = 10.85 V

FFh = 10.875 V

BOP_CFG2 (book=0x00 page=0x00 address=0x1D) [reset=4Eh]

BOP attack rate, attack step size and hold time.

Figure 84. BOP_CFG2 Register Address: 0x1D
76543210
BOP_ATK_RT[2:0]BOP_ATK_ST[1:0]BOP_HLD_TM[2:0]
RW-2hRW-1hRW-6h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 112. Brown Out Prevention 2 Field Descriptions

BitFieldTypeResetDescription
7-5BOP_ATK_RT[2:0]RW2hBrown out prevention attack rate.
000b = 5 us/step

001b = 10 us/step

010b = 20 us/step

011b = 40 us/step

100b = 80 us/step

101b = 160 us/step

110b = 320 us/step

111b = 640 us/step
4-3BOP_ATK_ST[1:0]RW1hBrown out prevention attack step size.
00b = 0.5 dB

01b = 1 dB

10b = 1.5 dB

11b = 2 dB
2-0BOP_HLD_TM[2:0]RW6hBrown out prevention hold time.
000b = 0 ms

001b = 10 ms

010b = 25 ms

011b = 50 ms

100b = 100 ms

101b = 250 ms

110b = 500 ms

111b = 1000 ms

ICLA_CFG0 (book=0x00 page=0x00 address=0x1E) [reset=0h]

ICLA starting time slot and enable.

Figure 85. ICLA_CFG0 Register Address: 0x1E
76543210
ICLA_USE_MAXICLA_SLOT[5:0]ICLA_EN
RW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 113. Inter Chip Limiter Alignment 0 Field Descriptions

BitFieldTypeResetDescription
7ICLA_USE_MAXRW0hInter chip limiter alignment min/max config
0b = Use the maximum of the ICLA group gain reduction

1b = Use the minimum of the ICLA group gain reduction
6-1ICLA_SLOT[5:0]RW0hInter chip limiter alignment starting time slot.
0ICLA_ENRW0hInter chip limiter alignment enable.
0b = Disabled

1b = Enabled

ICLA_CFG1 (book=0x00 page=0x00 address=0x1F) [reset=0h]

ICLA time slot enables.

Figure 86. ICLA_CFG1 Register Address: 0x1F
76543210
ICLA_SEN[7]ICLA_SEN[6]ICLA_SEN[5]ICLA_SEN[4]ICLA_SEN[3]ICLA_SEN[2]ICLA_SEN[1]ICLA_SEN[0]
RW-0hRW-0hRW-0hRW-0hRW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 114. Inter Chip Limiter Alignment 1 Field Descriptions

BitFieldTypeResetDescription
7ICLA_SEN[7]RW0hTime slot equals ICLA_SLOT[5:0]+7. When enabled, the limiter will include this time slot in the alignment group.
0b = Disabled

1b = Enabled
6ICLA_SEN[6]RW0hTime slot equals ICLA_SLOT[5:0]+6. When enabled, the limiter will include this time slot in the alignment group.
0b = Disabled

1b = Enabled
5ICLA_SEN[5]RW0hTime slot equals ICLA_SLOT[5:0]+5. When enabled, the limiter will include this time slot in the alignment group.
0b = Disabled

1b = Enabled
4ICLA_SEN[4]RW0hTime slot equals ICLA_SLOT[5:0]+4. When enabled, the limiter will include this time slot in the alignment group.
0b = Disabled

1b = Enabled
3ICLA_SEN[3]RW0hTime slot equals ICLA_SLOT[5:0]+3. When enabled, the limiter will include this time slot in the alignment group.
0b = Disabled

1b = Enabled
2ICLA_SEN[2]RW0hTime slot equals ICLA_SLOT[5:0]+2. When enabled, the limiter will include this time slot in the alignment group.
0b = Disabled

1b = Enabled
1ICLA_SEN[1]RW0hTime slot equals ICLA_SLOT[5:0]+1. When enabled, the limiter will include this time slot in the alignment group.
0b = Disabled

1b = Enabled
0ICLA_SEN[0]RW0hTime slot equals ICLA_SLOT[5:0]. When enabled, the limiter will include this time slot in the alignment group.
0b = Disabled

1b = Enabled

INT_MASK0 (book=0x00 page=0x00 address=0x20) [reset=FCh]

Interrupt masks.

Figure 87. INT_MASK0 Register Address: 0x20
76543210
INT_MASK[7]INT_MASK[6]INT_MASK[5]INT_MASK[4]INT_MASK[3]INT_MASK[2]INT_MASK[1]INT_MASK[0]
RW-1hRW-1hRW-1hRW-1hRW-1hRW-1hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 115. Interrupt Mask 0 Field Descriptions

BitFieldTypeResetDescription
7INT_MASK[7]RW1hLimiter mute mask.
0b = Don't Mask

1b = Mask
6INT_MASK[6]RW1hLimiter infinite hold mask.
0b = Don't Mask

1b = Mask
5INT_MASK[5]RW1hLimiter max attenuation mask.
0b = Don't Mask

1b = Mask
4INT_MASK[4]RW1hVBAT <N521 Inflection Point mask.
0b = Don't Mask

1b = Mask
3INT_MASK[3]RW1hLimiter active mask.
0b = Don't Mask

1b = Mask
2INT_MASK[2]RW1hTDM clock error mask.
0b = Don't Mask

1b = Mask
1INT_MASK[1]RW0hOver current error mask.
0b = Don't Mask

1b = Mask
0INT_MASK[0]RW0hOver temp error mask.
0b = Don't Mask

1b = Mask

INT_MASK1 (book=0x00 page=0x00 address=0x21) [reset=B1h]

Interrupt masks.

Figure 88. INT_MASK1 Register Address: 0x21
76543210
INT_MASK[14]ReservedReservedReservedINT_MASK[11]INT_MASK[10]INT_MASK[9]INT_MASK[8]
RW-1hRW-0hRW-1hRW-1hRW-0hRW-0hRW-0hRW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 116. Interrupt Mask 1 Field Descriptions

BitFieldTypeResetDescription
7INT_MASK[14]RW1hPDM audio data invalid mask.
0b = Don't Mask

1b = Mask
6ReservedRW0hReserved
5ReservedRW1hReserved
4ReservedRW1hReserved
3INT_MASK[11]RW0hVBAT OVLO mask.
0b = Don't Mask

1b = Mask
2INT_MASK[10]RW0hVBAT UVLO mask.
0b = Don't Mask

1b = Mask
1INT_MASK[9]RW0hVBAT Brown out mask
0b = Don't Mask

1b = Mask
0INT_MASK[8]RW1hPDM clock error mask.
0b = Don't Mask

1b = Mask

INT_LIVE0 (book=0x00 page=0x00 address=0x22) [reset=0h]

Live interrupt readback.

Figure 89. INT_LIVE0 Register Address: 0x22
76543210
INT_LIVE[7]INT_LIVE[6]INT_LIVE[5]INT_LIVE[4]INT_LIVE[3]INT_LIVE[2]INT_LIVE[1]INT_LIVE[0]
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 117. Live Interrupt Readback 0 Field Descriptions

BitFieldTypeResetDescription
7INT_LIVE[7]R0hInterrupt due to limiter mute.
0b = No interrupt

1b = Interrupt
6INT_LIVE[6]R0hInterrupt due to limiter infinite hold.
0b = No interrupt

1b = Interrupt
5INT_LIVE[5]R0hInterrupt due to limiter max attenuation.
0b = No interrupt

1b = Interrupt
4INT_LIVE[4]R0hInterrupt due to VBAT below limiter inflection point.
0b = No interrupt

1b = Interrupt
3INT_LIVE[3]R0hInterrupt due to limiter active.
0b = No interrupt

1b = Interrupt
2INT_LIVE[2]R0hInterrupt due to TDM clock error.
0b = No interrupt

1b = Interrupt
1INT_LIVE[1]R0hInterrupt due to over current error.
0b = No interrupt

1b = Interrupt
0INT_LIVE[0]R0hInterrupt due to over temp error.
0b = No interrupt

1b = Interrupt

INT_LIVE1 (book=0x00 page=0x00 address=0x23) [reset=0h]

Live interrupt readback.

Figure 90. INT_LIVE1 Register Address: 0x23
76543210
INT_LIVE[15]ReservedReservedReservedINT_LIVE[11]INT_LIVE[10]INT_LIVE[9]INT_LIVE[8]
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 118. Live Interrupt Readback 1 Field Descriptions

BitFieldTypeResetDescription
7INT_LIVE[15]R0hInterrupt due to PDM audio data invalid
0b = No interrupt

1b = Interrupt
6ReservedR0hReserved
5ReservedR0hReserved
4ReservedR0hReserved
3INT_LIVE[11]R0hInterrupt due to VBAT OVLO flag.
0b = No interrupt

1b = Interrupt
2INT_LIVE[10]R0hInterrupt due to VBAT UVLO flag.
0b = No interrupt

1b = Interrupt
1INT_LIVE[9]R0hInterrupt due to VBAT brown out flag.
0b = No interrupt

1b = Interrupt
0INT_LIVE[8]R0hInterrupt due to PDM clock error.
0b = No interrupt

1b = Interrupt

INT_LTCH0 (book=0x00 page=0x00 address=0x24) [reset=0h]

Latched interrupt readback.

Figure 91. INT_LTCH0 Register Address: 0x24
76543210
INT_LTCH[7]INT_LTCH[6]INT_LTCH[5]INT_LTCH[4]INT_LTCH[3]INT_LTCH[2]INT_LTCH[1]INT_LTCH[0]
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 119. Latched Interrupt Readback 0 Field Descriptions

BitFieldTypeResetDescription
7INT_LTCH[7]R0hInterrupt due to limiter mute (read to clear).
0b = No interrupt

1b = Interrupt
6INT_LTCH[6]R0hInterrupt due to limiter infinite hold (read to clear).
0b = No interrupt

1b = Interrupt
5INT_LTCH[5]R0hInterrupt due to limiter max attenuation (read to clear).
0b = No interrupt

1b = Interrupt
4INT_LTCH[4]R0hInterrupt due to VBAT < limiter inflection point (read to clear).
0b = No interrupt

1b = Interrupt
3INT_LTCH[3]R0hInterrupt due to limiter active (read to clear).
0b = No interrupt

1b = Interrupt
2INT_LTCH[2]R0hInterrupt due to TDM clock error (read to clear).
0b = No interrupt

1b = Interrupt
1INT_LTCH[1]R0hInterrupt due to over current error (read to clear).
0b = No interrupt

1b = Interrupt
0INT_LTCH[0]R0hInterrupt due to over temp error (read to clear).
0b = No interrupt

1b = Interrupt

INT_LTCH1 (book=0x00 page=0x00 address=0x25) [reset=0h]

Latched interrupt readback.

Figure 92. INT_LTCH1 Register Address: 0x25
76543210
INT_LTCH[15]ReservedReservedReservedINT_LTCH[11]INT_LTCH[10]INT_LTCH[9]INT_LTCH[8]
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 120. Latched Interrupt Readback 1 Field Descriptions

BitFieldTypeResetDescription
7INT_LTCH[15]R0hInterrupt due to PDM audio data invalid. (read to clear).
0b = No interrupt

1b = Interrupt
6ReservedR0hReserved
5ReservedR0hReserved
4ReservedR0hReserved
3INT_LTCH[11]R0hInterrupt due to VBAT OVLO flag (read to clear).
0b = No interrupt

1b = Interrupt
2INT_LTCH[10]R0hInterrupt due to VBAT UVLO flag (read to clear).
0b = No interrupt

1b = Interrupt
1INT_LTCH[9]R0hInterrupt due to VBAT brown out flag (read to clear).
0b = No interrupt

1b = Interrupt
0INT_LTCH[8]R0hInterrupt due to PDM clock error (read to clear).
0b = No interrupt

1b = Interrupt

INT_LTCH2 (book=0x00 page=0x00 address=0x26) [reset=0h]

Table 1. INT_LTCH2 Register Address: 0x26

76543210
INT_LTCH[23]INT_LTCH[22]INT_LTCH[21]INT_LTCH[20]INT_LTCH[19]INT_LTCH[18]INT_LTCH[17]INT_LTCH[16]
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 121. INT_LTCH2 Field Descriptions

BitFieldTypeResetDescription
7INT_LTCH[23]R0hInterrupt due to clock halt flag (read to clear)
0b = No interrupt
1b = Interrupt
6INT_LTCH[22]R0hInterrupt due to DMA Request to DSP lost flag (read to clear)
0b = No interrupt
1b = Interrupt
5INT_LTCH[21]R0hInterrupt due to Auto Trim converged status (read to clear)
0b = No interrupt
1b = Interrupt
4INT_LTCH[20]R0hInterrupt due to Class D Clamp status flag (read to clear)
0b = No interrupt
1b = Interrupt
3INT_LTCH[19]R0hInterrupt due to HIGH SIDE OC flag (read to clear).
0b = No interrupt
1b = Interrupt
2INT_LTCH[18]R0hInterrupt due to LOW SIDE OC flag (read to clear).
0b = No interrupt
1b = Interrupt
1INT_LTCH[17]R1hInterrupt due to LDO 5 V PG flag (read to clear).
0b = No interrupt
1b = Interrupt
0INT_LTCH[16]R0hInterrupt due to LDO 5 V OL (read to clear).
0b = No interrupt
1b = Interrupt

VBAT_MSB (book=0x00 page=0x00 address=0x27) [reset=0h]

MSBs of SAR ADC VBAT conversion.

Figure 93. VBAT_MSB Register Address: 0x27
76543210
VBAT_CNV[11:4]
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 122. SAR ADC Conversion 0 Field Descriptions

BitFieldTypeResetDescription
7--4VBAT_CNV[11:0]R0hReturns SAR ADC VBAT conversion MSBs.

VBAT_LSB (book=0x00 page=0x00 address=0x28) [reset=0h]

LSBs of SAR ADC VBAT conversion.

Figure 94. VBAT_LSB Register Address: 0x28
76543210
VBAT_CNV[3:0]Reserved
R-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 123. SAR ADC Conversion 1 Field Descriptions

BitFieldTypeResetDescription
7-4VBAT_CNV[3:0]R0hReturns SAR ADC VBAT conversion LSBs.
3-0ReservedR0hReserved

TEMP_MSB (book=0x00 page=0x00 address=0x29) [reset=0h]

SARD ADC Temp conversion.

Figure 95. TEMP_MSB Register Address: 0x29
76543210
TMP_CNV[11:4]
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 124. SAR ADC Conversion 2 Field Descriptions

BitFieldTypeResetDescription
7--4TMP_CNV[11:0]R0hReturns SAR ADC temp sensor conversion.

TEMP_LSB (book=0x00 page=0x00 address=0x2A) [reset=0h]

SARD ADC Temp conversion.

Figure 96. TEMP_LSB Register Address: 0x2A
76543210
TMP_CNV[3:0]Reserved
-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 125. SAR ADC Conversion 2 Field Descriptions

BitFieldTypeResetDescription
7-4TMP_CNV[3:0]0hReturns SAR ADC temp sensor conversion.
3-0ReservedR0hReserved

INT_CFG (book=0x00 page=0x00 address=0x30) [reset=5h]

Sets whether latched or live interrupts will trigger IRQZ pin.

Figure 97. INT_CFG Register Address: 0x30
76543210
ReservedIRQZ_PIN_CFG[1:0]
RW-0hRW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 126. Interrupt Configuration Field Descriptions

BitFieldTypeResetDescription
7-2ReservedRW0hReserved
1-0IRQZ_PIN_CFG[1:0]RW1hIRQZ interrupt configuration.
00b = IRQZ will assert on any unmasked live interrupts

01b = IRQZ will assert on any unmasked latched interrupts

10b = IRQZ will assert for 2ms one time on any unmasked live interrupt event

11b = IRQZ will assert for 2ms every 4ms on any unmasked latched interrupts

DIN_PD (book=0x00 page=0x00 address=0x31) [reset=0h]

Sets enables of input pin weak pull down.

Figure 98. DIN_PD Register Address: 0x31
76543210
DIN_PD[7]DIN_PD[6]DIN_PD[5]DIN_PD[4]ReservedDIN_PD[2]ReservedDIN_PD[0]
RW-0hRW-0hRW-0hRW-0hRW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 127. Digital Input Pin Pull Down Field Descriptions

BitFieldTypeResetDescription
7DIN_PD[7]RW0hWeak pull down for SDOUT
0b = Disabled

1b = Enabled
6DIN_PD[6]RW0hWeak pull down for SDIN.
0b = Disabled

1b = Enabled
5DIN_PD[5]RW0hWeak pull down for FSYNC.
0b = Disabled

1b = Enabled
4DIN_PD[4]RW0hWeak pull down for SBCLK.
0b = Disabled

1b = Enabled
3ReservedRW0hReserved
2DIN_PD[2]RW0hWeak pull down for PDMD1.
0b = Disabled

1b = Enabled
0ReservedRW0hReserved
0DIN_PD[0]RW0hWeak pull down for PDMCK1.
0b = Disabled

1b = Enabled

MISC_IRQ (book=0x00 page=0x00 address=0x32) [reset=81h]

Set IRQZ pin active state

Figure 99. MISC_IRQ Register Address: 0x32
76543210
IRQZ_POLReservedReservedReservedReservedIRQZ_VAL
RW-1hRW-0hRW-0hRW-0hRW-0hR-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 128. Misc Configuration Field Descriptions

BitFieldTypeResetDescription
7IRQZ_POLRW1hIRQZ pin polarity for interrupt.
0b = Active high (IRQ)

1b = Active low (IRQZ)
6-4ReservedRW0hReserved
3ReservedRW0hReserved
2ReservedRW0hReserved
1ReservedRW0hReserved
0IRQZ_VALR1hIRQZ bit bang in read value. Default is 1b'1 if there are no interupts/errors
0b = IRQZ Input Buffer Value=0

1b = IRQZ Input Buffer Value=1

CLOCK_CFG (book=0x00 page=0x00 address=0x3C) [reset=Dh]

Can override audio configure and set the clocking ratio

Figure 100. CLOCK_CFG Register Address: 0x3C
76543210
ReservedReservedSBCLK_FS_RATIO[3:0]AUTO_CLK[1:0]
RW-0hRW-0hRW-3hRW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 129. Clock Configuration Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6ReservedRW0hReserved
5-2SBCLK_FS_RATIO[3:0]RW3hProgram manually SBCLK to FS ratio when auto clock detection is disabled
00h = 16

01h = 24

02h = 32

03h = 48

04h = 64

05h = 96

06h = 128

07h = 192

08h = 256

09h = 384

0Ah = 512
1-0AUTO_CLK[1:0]RW1hClocking automatic configuraiton
00b = Auto configure clock dividers based on SBCLK to FSYNC ratio

01b = Manually configure clock dividers by programming SBCLK_FS_RATIO

TDM_DET (book=0x00 page=0x00 address=0x77) [reset=7Fh]

Readback of internal auto-rate detection.

Figure 101. TDM_DET Register Address: 0x77
76543210
ReservedFS_RATIO[3:0]FS_RATE_V[2:0]
R-0hR-FhR-7h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 130. TDM Clock detection monitor Field Descriptions

BitFieldTypeResetDescription
7ReservedR0hReserved
6-3FS_RATIO[3:0]RFhDetected SBCLK to FSYNC ratio.
00h = 16

01h = 24

02h = 32

03h = 48

04h = 64

05h = 96

06h = 128

07h = 192

08h = 256

09h = 384

0Ah = 512

0Bh-0Eh = Reserved

0F = Invalid ratio
2-0FS_RATE_V[2:0]R7hDetected sample rate of TDM bus.
000b = 7.35/8 KHz

001b = 14.7/16 KHz

010b = 29.4/32 KHz

011b = 44.1/48 KHz

100b = 88.2/96 kHz

101b = 176.4/192 kHz

110b = reserved

111b = Error condition

REV_ID (book=0x00 page=0x00 address=0x7D) [reset=20h]

Returns REV and PG ID.

Figure 102. REV_ID Register Address: 0x7D
76543210
REV_ID[3:0]PG_ID[3:0]
R-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 131. Revision and PG ID Field Descriptions

BitFieldTypeResetDescription
7-4REV_ID[3:0]R0hReturns the revision ID.
3-0PG_ID[3:0]R0hReturns the PG ID.

I2C_CKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]

Returns I2C checksum.

Figure 103. I2C_CKSUM Register Address: 0x7E
76543210
I2C_CKSUM[7:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 132. I2C Checksum Field Descriptions

BitFieldTypeResetDescription
7-0I2C_CKSUM[7:0]RW0hReturns I2C checksum. Writing to this register will reset the checksum to the written value. This register is updated on writes to other registers on all books and pages.

BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]

Device's memory map is divided into pages and books. This register sets the book.

Figure 104. BOOK Register Address: 0x7F
76543210
BOOK[7:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 133. Device Book Field Descriptions

BitFieldTypeResetDescription
7-0BOOK[7:0]RW0hSets the device book.
00h = Book 0

01h = Book 1

...

FFh = Book 255