SLASEM6A October 2017  – December 2017 TAS2770


  1. 1     Features
  2. 2     Applications
  3. 3     Description
  4. DeviceImages
    1. FunctionalBlock Diagram
  5. 4     Revision History
  6. 5     Pin Configuration and Functions
    1. PinFunctions
  7. 6     Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6I2C Timing Requirements
    7. 6.7TDM Port Timing Requirements
    8. 6.8PDM Port Timing Requirements
    9. 6.9Typical Characteristics
  8. 7     Parameter Measurement Information
  9. 8     Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1Device Mode and Address Selection
      2. 8.3.2General I2C Operation
      3. 8.3.3Single-Byte and Multiple-Byte Transfers
      4. 8.3.4Single-Byte Write
      5. 8.3.5Multiple-Byte Write and Incremental Multiple-Byte Write
      6. 8.3.6Single-Byte Read
      7. 8.3.7Multiple-Byte Read
      8. 8.3.8Register Organization
    4. 8.4Device Functional Modes
      1. 8.4.1PDM Input
      2. 8.4.2TDM Port
      3. 8.4.3Playback Signal Path
        1. Pass Filter
        2. Volume Control and Amplifier Output Level
        3. Audio Playback Selection
        4. Tracking Limiter with Brown Out Prevention
        5. Chip Limiter Alignment
          1. Mode
        6. Settings
      4. 8.4.4 SAR ADC
      5. 8.4.5IV Sense
      6. 8.4.6Clocks and PLL
    5. 8.5Operational Modes
      1. 8.5.1Hardware Shutdown
      2. 8.5.2Software Shutdown
      3. 8.5.3Mute
      4. 8.5.4Active
      5. 8.5.5Mode Control and Software Reset
    6. 8.6Faults and Status
    7. 8.7Power Sequencing Requirements
    8. 8.8Digital Input Pull Downs
    9. 8.9Register Maps
      1. 8.9.1Register Summary Table Book=0x00 Page=0x00
      2. 8.9.2Register Maps
        1. PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
          1. Table82. Device Page Field Descriptions
        2. SW_RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
          1. Table83. Software Reset Field Descriptions
        3. PWR_CTL (book=0x00 page=0x00 address=0x02) [reset=Eh]
          1. Table84. Power Control Field Descriptions
        4. PB_CFG0 (book=0x00 page=0x00 address=0x03) [reset=10h]
          1. Table85. Playback Configuration 0 Field Descriptions
        5. PB_CFG1 (book=0x00 page=0x00 address=0x04) [reset=1h]
          1. Table86. Playback Configuration 1 Field Descriptions
        6. PB_CFG2 (book=0x00 page=0x00 address=0x05) [reset=0h]
          1. Table87. Playback Configuration 2 Field Descriptions
        7. PB_CFG3 (book=0x00 page=0x00 address=0x06) [reset=0h]
          1. Table88. Playback Configuration 3 Field Descriptions
        8. MISC_CFG (book=0x00 page=0x00 address=0x07) [reset=6h]
          1. Table89. Misc Configuration Field Descriptions
        9. PDM_CFG0 (book=0x00 page=0x00 address=0x08) [reset=0h]
          1. Table90. PDM Input Register 0 Field Descriptions
        10. (book=0x00 page=0x00 address=0x09) [reset=8h]
          1. Table91. PDM Configuration 1 Field Descriptions
        11. (book=0x00 page=0x00 address=0x0A) [reset=7h]
          1. Table92. TDM Configuration 0 Field Descriptions
        12. (book=0x00 page=0x00 address=0x0B) [reset=2h]
          1. Table93. TDM Configuration 1 Field Descriptions
        13. (book=0x00 page=0x00 address=0x0C) [reset=Ah]
          1. Table94. TDM Configuration 2 Field Descriptions
        14. (book=0x00 page=0x00 address=0x0D) [reset=10h]
          1. Table95. TDM Configuration 3 Field Descriptions
        15. (book=0x00 page=0x00 address=0x0E) [reset=13h]
          1. Table96. TDM Configuration 4 Field Descriptions
        16. (book=0x00 page=0x00 address=0x0F) [reset=2h]
          1. Table97. TDM Configuration 5 Field Descriptions
        17. (book=0x00 page=0x00 address=0x10) [reset=0h]
          1. Table98. TDM Configuration 6 Field Descriptions
        18. (book=0x00 page=0x00 address=0x11) [reset=4h]
          1. Table99. TDM Configuration 7 Field Descriptions
        19. (book=0x00 page=0x00 address=0x12) [reset=6h]
          1. Table100. TDM Configuration 8 Field Descriptions
        20. (book=0x00 page=0x00 address=0x13) [reset=7h]
          1. Table101. TDM Configuration 9 Field Descriptions
        21. (book=0x00 page=0x00 address=0x14) [reset=8h]
          1. Table102. TDM Configuration 10 Field Descriptions
        22. (book=0x00 page=0x00 address=0x15) [reset=14h]
          1. Table103. Limiter Configuration 0 Field Descriptions
        23. (book=0x00 page=0x00 address=0x16) [reset=76h]
          1. Table104. Limiter Configuration 1 Field Descriptions
        24. (book=0x00 page=0x00 address=0x17) [reset=10h]
          1. Table105. Limiter Configuration 2 Field Descriptions
        25. (book=0x00 page=0x00 address=0x18) [reset=6Eh]
          1. Table106. Limiter Configuration 3 Field Descriptions
        26. (book=0x00 page=0x00 address=0x19) [reset=1Eh]
          1. Table107. Limiter Configuration 4 Field Descriptions
        27. (book=0x00 page=0x00 address=0x1A) [reset=58h]
          1. Table108. Limiter Configuration 5 Field Descriptions
        28. (book=0x00 page=0x00 address=0x1B) [reset=1h]
          1. Table109. Brown Out Prevention 0 Field Descriptions
        29. (book=0x00 page=0x00 address=0x1C) [reset=14h]
          1. Table110. Brown Out Prevention 1 Field Descriptions
        30. (book=0x00 page=0x00 address=0x1D) [reset=4Eh]
          1. Table111. Brown Out Prevention 2 Field Descriptions
        31. (book=0x00 page=0x00 address=0x1E) [reset=0h]
          1. Table112. Inter Chip Limiter Alignment 0 Field Descriptions
        32. (book=0x00 page=0x00 address=0x1F) [reset=0h]
          1. Table113. Inter Chip Limiter Alignment 1 Field Descriptions
        33. (book=0x00 page=0x00 address=0x20) [reset=FCh]
          1. Table114. Interrupt Mask 0 Field Descriptions
        34. (book=0x00 page=0x00 address=0x21) [reset=B1h]
          1. Table115. Interrupt Mask 1 Field Descriptions
        35. (book=0x00 page=0x00 address=0x22) [reset=0h]
          1. Table116. Live Interrupt Readback 0 Field Descriptions
        36. (book=0x00 page=0x00 address=0x23) [reset=0h]
          1. Table117. Live Interrupt Readback 1 Field Descriptions
        37. (book=0x00 page=0x00 address=0x24) [reset=0h]
          1. Table118. Latched Interrupt Readback 0 Field Descriptions
        38. (book=0x00 page=0x00 address=0x25) [reset=0h]
          1. Table119. Latched Interrupt Readback 1 Field Descriptions
        39. (book=0x00 page=0x00 address=0x26) [reset=0h]
          1. Table1. INT_LTCH2 Register Address: 0x26
          2. Table120. INT_LTCH2 Field Descriptions
        40. (book=0x00 page=0x00 address=0x27) [reset=0h]
          1. Table121. SAR ADC Conversion 0 Field Descriptions
        41. (book=0x00 page=0x00 address=0x28) [reset=0h]
          1. Table122. SAR ADC Conversion 1 Field Descriptions
        42. (book=0x00 page=0x00 address=0x29) [reset=0h]
          1. Table123. SAR ADC Conversion 2 Field Descriptions
        43. (book=0x00 page=0x00 address=0x2A) [reset=0h]
          1. Table124. SAR ADC Conversion 2 Field Descriptions
        44. (book=0x00 page=0x00 address=0x30) [reset=5h]
          1. Table125. Interrupt Configuration Field Descriptions
        45. (book=0x00 page=0x00 address=0x31) [reset=0h]
          1. Table126. Digital Input Pin Pull Down Field Descriptions
        46. (book=0x00 page=0x00 address=0x32) [reset=81h]
          1. Table127. Misc Configuration Field Descriptions
        47. (book=0x00 page=0x00 address=0x3C) [reset=Dh]
          1. Table128. Clock Configuration Field Descriptions
        48. (book=0x00 page=0x00 address=0x77) [reset=7Fh]
          1. Table129. TDM Clock detection monitor Field Descriptions
        49. (book=0x00 page=0x00 address=0x7D) [reset=20h]
          1. Table130. Revision and PG ID Field Descriptions
        50. (book=0x00 page=0x00 address=0x7E) [reset=0h]
          1. Table131. I2C Checksum Field Descriptions
        51. (book=0x00 page=0x00 address=0x7F) [reset=0h]
          1. Table132. Device Book Field Descriptions
  10. 9     Application and Implementation
    1. 9.1Application Information
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
      2. 9.2.2Detailed Design Procedure
        2. Input Capacitance
        3. Decoupling Capacitors
        4. Bootstrap Capacitors
      3. 9.2.3Application Curves
    3. 9.3Initialization Set Up
      1. 9.3.1Initial Device Configuration - Auto Rate
      2. 9.3.2Initial Device Configuration - 48 kHz
      3. 9.3.3Initial Device Configuration - 44.1 kHz
      4. 9.3.4Sample Rate Change - 48 kHz to 44.1kHz
      5. 9.3.5Sample Rate Change - 44.1 kHz to 48 kHz
      6. 9.3.6Device Mute
      7. 9.3.7Device Un-Mute
      8. 9.3.8Device Sleep
      9. 9.3.9Device Wake
  11. 10    Power Supply Recommendations
  12. 11    Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  13. 12    Device and Documentation Support
    1. 12.1Receiving Notification of Documentation Updates
    2. 12.2Community Resources
    3. 12.3Trademarks
    4. 12.4Electrostatic Discharge Caution
    5. 12.5Glossary
  14. 13    Mechanical, Packaging, and Orderable Information
    1. 13.1Package Option Addendum
      1. 13.1.1Packaging Information
      2. 13.1.2Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YFF|30
  • RJQ|26
Orderable Information

Faults and Status

During the power-up sequence, the power-on-reset circuit (POR) monitoring the AVDD pin will hold the device in reset (including all configuration registers) until the supply is valid. The device will not exit hardware shutdown until AVDD is valid and the SDZ pin is released. Once SDZ is released, the digital core voltage regulator will power up, enabling detection of the operational mode. If AVDD dips below the POR threshold, the device will immediately be forced into a reset state.

The device also monitors the VBAT supply and holds the analog core in power down if the supply is below the UVLO threshold or above the OVLO threshold. If the TAS2770 is in active operation and a UVLO or OVLO fault occurs, the analog supplies will immediately power down to protect the device. These faults are latching and require a transition through HW/SW shutdown to clear the fault. The live and latched registers will report UVLO/OVLO faults.

The device transitions into software shutdown mode if it detects any faults with the TDM clocks such as:

• Invalid SBCLK to FSYNC ratio

• Invalid FSYNC frequency

• Halting of SBCLK or FSYNC clocks

Upon detection of a TDM clock error, the device transitions into software shutdown mode as quickly as possible to limit the possibility of audio artifacts. Once all TDM clock errors are resolved, the device volume ramps back to its previous playback state. During a TDM clock error, the IRQZ pin will assert low if the clock error interrupt mask register bit is set low (INT_MASK[2]). The clock fault is also available for readback in the live or latched fault status registers (INT_LIVE[2] and INT_LTCH[2]). Reading the latched fault status register (INT_LTCH[7:0]) clears the register.

The TAS2770 also monitors die temperature and Class-D load current and will enter software shutdown mode if either of these exceed safe values. As with the TDM clock error, the IRQZ pin will assert low for these faults if the appropriate fault interrupt mask register bit is set low (INT_MASK[0] for over temp and INT_MASK[1] for over current). The fault status can also be monitored in the live and latched fault registers as with the TDM clock error.

Die over temp and Class-D over current errors can either be latching (i.e. the device will enter software shutdown until a HW/SW shutdown sequence is applied) or they can be configured to automatically retry after a prescribed time. This behavior can be configured in the OTE_RETRY and OCE_RETRY register bits (for over temp and over current respectively). Even in latched mode, the Class-D will not attempt to retry after an over temp or over current error until the retry time period (1.5s) has elapsed. This prevents applying repeated stress to the device in a rapid fashion that could lead to device damage. If the device has been cycled through SW/HW shutdown, the device will only begin to operate after the retry time period.

The status registers (and IRQZ pin if enabled via the status mask register) also indicates limiter behavior including when the limiter is activity, when VBAT is below the inflection point, when maximum attenuation has been applied, when the limiter is in infinite hold and when the limiter has muted the audio.

The IRQZ pin is an open drain output that asserts low during unmasked fault conditions and therefore must be pulled up with a resistor to IOVDD. An internal pull up resistor is provided in the TAS2770 and can be accessed by setting the IRQZ_PU register bit high. Figure 54 below highlights the IRQZ pin circuit.

TAS2770 tas5770l_faultz_circuit.gifFigure 54. IRQZ Pin

Table 78. Fault Interrupt Mask

INT_MASK[10:0] BitInterruptDefault (1 = Mask)
0Over Temp Error0
1Over Current Error0
2TDM Clock Error1
3Limiter Active1
4VBAT < Inf Point1
5Limiter Max Atten1
6Limiter Inf Hold1
7Limiter Mute1
8PDM Clock Error1
9VBAT Brown Out1

Table 79. IRQZ Internal Pull Up Enable

0Disabled (default)

Table 80. IRQZ Interrupt Configuration

00IRQZ will assert on any unmasked live interrupts
01IRQZ will assert on any unmasked latched interrupts (default)