SLASEM6A October 2017  – December 2017 TAS2770

PRODUCTION DATA. 

  1. 1     Features
  2. 2     Applications
  3. 3     Description
  4. DeviceImages
    1. FunctionalBlock Diagram
  5. 4     Revision History
  6. 5     Pin Configuration and Functions
    1. PinFunctions
  7. 6     Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6I2C Timing Requirements
    7. 6.7TDM Port Timing Requirements
    8. 6.8PDM Port Timing Requirements
    9. 6.9Typical Characteristics
  8. 7     Parameter Measurement Information
  9. 8     Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1Device Mode and Address Selection
      2. 8.3.2General I2C Operation
      3. 8.3.3Single-Byte and Multiple-Byte Transfers
      4. 8.3.4Single-Byte Write
      5. 8.3.5Multiple-Byte Write and Incremental Multiple-Byte Write
      6. 8.3.6Single-Byte Read
      7. 8.3.7Multiple-Byte Read
      8. 8.3.8Register Organization
    4. 8.4Device Functional Modes
      1. 8.4.1PDM Input
      2. 8.4.2TDM Port
      3. 8.4.3Playback Signal Path
        1. 8.4.3.1High Pass Filter
        2. 8.4.3.2Digital Volume Control and Amplifier Output Level
        3. 8.4.3.3 Audio Playback Selection
        4. 8.4.3.4Battery Tracking Limiter with Brown Out Prevention
        5. 8.4.3.5Inter Chip Limiter Alignment
          1. 8.4.3.5.1TDM Mode
        6. 8.4.3.6Class-D Settings
      4. 8.4.4 SAR ADC
      5. 8.4.5IV Sense
      6. 8.4.6Clocks and PLL
    5. 8.5Operational Modes
      1. 8.5.1Hardware Shutdown
      2. 8.5.2Software Shutdown
      3. 8.5.3Mute
      4. 8.5.4Active
      5. 8.5.5Mode Control and Software Reset
    6. 8.6Faults and Status
    7. 8.7Power Sequencing Requirements
    8. 8.8Digital Input Pull Downs
    9. 8.9Register Maps
      1. 8.9.1Register Summary Table Book=0x00 Page=0x00
      2. 8.9.2Register Maps
        1. 8.9.2.1 PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
          1. Table82. Device Page Field Descriptions
        2. 8.9.2.2 SW_RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
          1. Table83. Software Reset Field Descriptions
        3. 8.9.2.3 PWR_CTL (book=0x00 page=0x00 address=0x02) [reset=Eh]
          1. Table84. Power Control Field Descriptions
        4. 8.9.2.4 PB_CFG0 (book=0x00 page=0x00 address=0x03) [reset=10h]
          1. Table85. Playback Configuration 0 Field Descriptions
        5. 8.9.2.5 PB_CFG1 (book=0x00 page=0x00 address=0x04) [reset=1h]
          1. Table86. Playback Configuration 1 Field Descriptions
        6. 8.9.2.6 PB_CFG2 (book=0x00 page=0x00 address=0x05) [reset=0h]
          1. Table87. Playback Configuration 2 Field Descriptions
        7. 8.9.2.7 PB_CFG3 (book=0x00 page=0x00 address=0x06) [reset=0h]
          1. Table88. Playback Configuration 3 Field Descriptions
        8. 8.9.2.8 MISC_CFG (book=0x00 page=0x00 address=0x07) [reset=6h]
          1. Table89. Misc Configuration Field Descriptions
        9. 8.9.2.9 PDM_CFG0 (book=0x00 page=0x00 address=0x08) [reset=0h]
          1. Table90. PDM Input Register 0 Field Descriptions
        10. 8.9.2.10PDM_CFG1 (book=0x00 page=0x00 address=0x09) [reset=8h]
          1. Table91. PDM Configuration 1 Field Descriptions
        11. 8.9.2.11TDM_CFG0 (book=0x00 page=0x00 address=0x0A) [reset=7h]
          1. Table92. TDM Configuration 0 Field Descriptions
        12. 8.9.2.12TDM_CFG1 (book=0x00 page=0x00 address=0x0B) [reset=2h]
          1. Table93. TDM Configuration 1 Field Descriptions
        13. 8.9.2.13TDM_CFG2 (book=0x00 page=0x00 address=0x0C) [reset=Ah]
          1. Table94. TDM Configuration 2 Field Descriptions
        14. 8.9.2.14TDM_CFG3 (book=0x00 page=0x00 address=0x0D) [reset=10h]
          1. Table95. TDM Configuration 3 Field Descriptions
        15. 8.9.2.15TDM_CFG4 (book=0x00 page=0x00 address=0x0E) [reset=13h]
          1. Table96. TDM Configuration 4 Field Descriptions
        16. 8.9.2.16TDM_CFG5 (book=0x00 page=0x00 address=0x0F) [reset=2h]
          1. Table97. TDM Configuration 5 Field Descriptions
        17. 8.9.2.17TDM_CFG6 (book=0x00 page=0x00 address=0x10) [reset=0h]
          1. Table98. TDM Configuration 6 Field Descriptions
        18. 8.9.2.18TDM_CFG7 (book=0x00 page=0x00 address=0x11) [reset=4h]
          1. Table99. TDM Configuration 7 Field Descriptions
        19. 8.9.2.19TDM_CFG8 (book=0x00 page=0x00 address=0x12) [reset=6h]
          1. Table100. TDM Configuration 8 Field Descriptions
        20. 8.9.2.20TDM_CFG9 (book=0x00 page=0x00 address=0x13) [reset=7h]
          1. Table101. TDM Configuration 9 Field Descriptions
        21. 8.9.2.21TDM_CFG10 (book=0x00 page=0x00 address=0x14) [reset=8h]
          1. Table102. TDM Configuration 10 Field Descriptions
        22. 8.9.2.22LIM_CFG0 (book=0x00 page=0x00 address=0x15) [reset=14h]
          1. Table103. Limiter Configuration 0 Field Descriptions
        23. 8.9.2.23LIM_CFG1 (book=0x00 page=0x00 address=0x16) [reset=76h]
          1. Table104. Limiter Configuration 1 Field Descriptions
        24. 8.9.2.24LIM_CFG2 (book=0x00 page=0x00 address=0x17) [reset=10h]
          1. Table105. Limiter Configuration 2 Field Descriptions
        25. 8.9.2.25LIM_CFG3 (book=0x00 page=0x00 address=0x18) [reset=6Eh]
          1. Table106. Limiter Configuration 3 Field Descriptions
        26. 8.9.2.26LIM_CFG4 (book=0x00 page=0x00 address=0x19) [reset=1Eh]
          1. Table107. Limiter Configuration 4 Field Descriptions
        27. 8.9.2.27LIM_CFG5 (book=0x00 page=0x00 address=0x1A) [reset=58h]
          1. Table108. Limiter Configuration 5 Field Descriptions
        28. 8.9.2.28BOP_CFG0 (book=0x00 page=0x00 address=0x1B) [reset=1h]
          1. Table109. Brown Out Prevention 0 Field Descriptions
        29. 8.9.2.29BOP_CFG1 (book=0x00 page=0x00 address=0x1C) [reset=14h]
          1. Table110. Brown Out Prevention 1 Field Descriptions
        30. 8.9.2.30BOP_CFG2 (book=0x00 page=0x00 address=0x1D) [reset=4Eh]
          1. Table111. Brown Out Prevention 2 Field Descriptions
        31. 8.9.2.31ICLA_CFG0 (book=0x00 page=0x00 address=0x1E) [reset=0h]
          1. Table112. Inter Chip Limiter Alignment 0 Field Descriptions
        32. 8.9.2.32ICLA_CFG1 (book=0x00 page=0x00 address=0x1F) [reset=0h]
          1. Table113. Inter Chip Limiter Alignment 1 Field Descriptions
        33. 8.9.2.33INT_MASK0 (book=0x00 page=0x00 address=0x20) [reset=FCh]
          1. Table114. Interrupt Mask 0 Field Descriptions
        34. 8.9.2.34INT_MASK1 (book=0x00 page=0x00 address=0x21) [reset=B1h]
          1. Table115. Interrupt Mask 1 Field Descriptions
        35. 8.9.2.35INT_LIVE0 (book=0x00 page=0x00 address=0x22) [reset=0h]
          1. Table116. Live Interrupt Readback 0 Field Descriptions
        36. 8.9.2.36INT_LIVE1 (book=0x00 page=0x00 address=0x23) [reset=0h]
          1. Table117. Live Interrupt Readback 1 Field Descriptions
        37. 8.9.2.37INT_LTCH0 (book=0x00 page=0x00 address=0x24) [reset=0h]
          1. Table118. Latched Interrupt Readback 0 Field Descriptions
        38. 8.9.2.38INT_LTCH1 (book=0x00 page=0x00 address=0x25) [reset=0h]
          1. Table119. Latched Interrupt Readback 1 Field Descriptions
        39. 8.9.2.39INT_LTCH2 (book=0x00 page=0x00 address=0x26) [reset=0h]
          1. Table1. INT_LTCH2 Register Address: 0x26
          2. Table120. INT_LTCH2 Field Descriptions
        40. 8.9.2.40VBAT_MSB (book=0x00 page=0x00 address=0x27) [reset=0h]
          1. Table121. SAR ADC Conversion 0 Field Descriptions
        41. 8.9.2.41VBAT_LSB (book=0x00 page=0x00 address=0x28) [reset=0h]
          1. Table122. SAR ADC Conversion 1 Field Descriptions
        42. 8.9.2.42TEMP_MSB (book=0x00 page=0x00 address=0x29) [reset=0h]
          1. Table123. SAR ADC Conversion 2 Field Descriptions
        43. 8.9.2.43TEMP_LSB (book=0x00 page=0x00 address=0x2A) [reset=0h]
          1. Table124. SAR ADC Conversion 2 Field Descriptions
        44. 8.9.2.44INT_CFG (book=0x00 page=0x00 address=0x30) [reset=5h]
          1. Table125. Interrupt Configuration Field Descriptions
        45. 8.9.2.45DIN_PD (book=0x00 page=0x00 address=0x31) [reset=0h]
          1. Table126. Digital Input Pin Pull Down Field Descriptions
        46. 8.9.2.46MISC_IRQ (book=0x00 page=0x00 address=0x32) [reset=81h]
          1. Table127. Misc Configuration Field Descriptions
        47. 8.9.2.47CLOCK_CFG (book=0x00 page=0x00 address=0x3C) [reset=Dh]
          1. Table128. Clock Configuration Field Descriptions
        48. 8.9.2.48TDM_DET (book=0x00 page=0x00 address=0x77) [reset=7Fh]
          1. Table129. TDM Clock detection monitor Field Descriptions
        49. 8.9.2.49REV_ID (book=0x00 page=0x00 address=0x7D) [reset=20h]
          1. Table130. Revision and PG ID Field Descriptions
        50. 8.9.2.50I2C_CKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]
          1. Table131. I2C Checksum Field Descriptions
        51. 8.9.2.51BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
          1. Table132. Device Book Field Descriptions
  10. 9     Application and Implementation
    1. 9.1Application Information
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
      2. 9.2.2Detailed Design Procedure
        1. 9.2.2.1Overview
        2. 9.2.2.2Select Input Capacitance
        3. 9.2.2.3Select Decoupling Capacitors
        4. 9.2.2.4Select Bootstrap Capacitors
      3. 9.2.3Application Curves
    3. 9.3Initialization Set Up
      1. 9.3.1Initial Device Configuration - Auto Rate
      2. 9.3.2Initial Device Configuration - 48 kHz
      3. 9.3.3Initial Device Configuration - 44.1 kHz
      4. 9.3.4Sample Rate Change - 48 kHz to 44.1kHz
      5. 9.3.5Sample Rate Change - 44.1 kHz to 48 kHz
      6. 9.3.6Device Mute
      7. 9.3.7Device Un-Mute
      8. 9.3.8Device Sleep
      9. 9.3.9Device Wake
  11. 10    Power Supply Recommendations
  12. 11    Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  13. 12    Device and Documentation Support
    1. 12.1Receiving Notification of Documentation Updates
    2. 12.2Community Resources
    3. 12.3Trademarks
    4. 12.4Electrostatic Discharge Caution
    5. 12.5Glossary
  14. 13    Mechanical, Packaging, and Orderable Information
    1. 13.1Package Option Addendum
      1. 13.1.1Packaging Information
      2. 13.1.2Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YFF|30
  • RJQ|26
Orderable Information

Specifications

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MINMAXUNIT
Supply VoltageAVDD–0.32V
IOVDD–0.32V
VBAT–0.319V
Input voltage(2)Digital IOs referenced to IOVDD supply–0.32.3V
Operating free-air temperature, TA ; Device is functional and reliable, some performance characteristics may be degraded.–4085°C
Performance free-air temperature, TP ; All performance characteristics are met.–2070°C
Operating junction temperature, TJ –40150°C
Storage temperature, Tstg–65150°C
Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Procedures. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.
All digital inputs and IOs are failsafe.

ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)±2500V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MINNOMMAXUNIT
AVDD Supply voltage1.651.81.95V
IOVDD Supply voltage1.651.81.95V
VBAT Supply voltage4.516V
VIH High-level digital input voltageIOVDDV
VIL Low-level digital input voltage0V
RSPK Minimum speaker impedance3.2Ω
LSPK Minimum speaker inductance10µH

Thermal Information

THERMAL METRIC(1)TAS2770UNIT
QFN (RJQ)
26 PINS
RθJAJunction-to-ambient thermal resistance 57.0°C/W
RθJC(top)Junction-to-case (top) thermal resistance 0.3°C/W
RθJBJunction-to-board thermal resistance 8.5°C/W
ψJTJunction-to-top characterization parameter 0.2°C/W
ψJBJunction-to-board characterization parameter 8.7°C/W
RθJC(bot)Junction-to-case (bottom) thermal resistance NA°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

Electrical Characteristics

TA = 25 °C, VBAT = 12.6 V, AVDD = IOVDD = 1.8 V, RL = 4 Ω + 33 µH, fin = 1 kHz, SSM, fs = 48 kHz, Gain = 21 dBV, SDZ = 1, Measured filter free using Parameter Measurement Information (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
DIGITAL INPUT and OUTPUT
VIH High-level digital input logic voltage threshold All digital pins except SDA and SCL; IOVDD = 1.8 V. 0.65 × IOVDDV
VIL Low-level digital input logic voltage threshold All digital pins except SDA and SCL; IOVDD = 1.8 V. 0.35 × IOVDDV
VIH(I2C) High-level digital input logic voltage threshold SDA and SCL; IOVDD = 1.8 V. 0.7 x IOVDD V
VIL(I2C) Low-level digital input logic voltage threshold SDA and SCL; IOVDD = 1.8 V. 0.3 x IOVDDV
VOH High-level digital output voltage All digital pins except SDA, SCL and IRQZ; IOVDD = 1.8 V; IOH = 2 mA. IOVDD – 0.45 VV
VOL Low-level digital output voltage All digital pins except SDA, SCL and IRQZ; IOVDD = 1.8 V; IOL = –2 mA. 0.45V
VOL(I2C) Low-level digital output voltage SDA and SCL; IOVDD = 1.8 V; IOL(I2C) = –2 mA. 0.2 x IOVDDV
VOL(IRQZ) Low-level digital output voltage for IRQZ open drain Output IRQZ; IOVDD = 1.8 V; IOL(IRQZ) = –2 mA. 0.45 V
IIH Input logic-high leakage for digital inputs All digital pins; Input = IOVDD. –5 0.1 5µA
IIL Input logic-low leakage for digital inputs All digital pins; Input = GND. –5 0.1 5µA
CIN Input capacitance for digital inputs All digital pins 5 pF
RPD Pull down resistance for digital input/IO pins when asserted on SDOUT, SDIN, FSYNC, SBCLK, PDMD, PDMCK 18
TDM SERIAL AUDIO PORT
PCM Sample Rates & FSYNC Input FrequencySingle Speed, I2S/TDM Operation48 kHz
Double Speed, I2S/TDM Operation 96
Quadruple Speed, I2S/TDM Operation192
SBCLK Input Frequency I2S/TDM Operation 2.54 27.1MHz
SBCLK Maximum Input Jitter RMS Jitter below 40 kHz that can be tolerated without performance degradation1ns
RMS Jitter above 40 kHz that can be tolerated without performance degradation10
SBCLK Cycles per FSYNC in I2S and TDM Modes Values: 64, 96, 128, 192, 256, 384 and 512 64 512Cycles
PDM AUDIO PORT
PDM clock input frequency Single Rate PDM 3.072MHz
Double Rate PDM6.144
PDM sensor clock rate to PCM sample rate oversampling ratios Single Speed PCM. Values: 64X and 128X.64128
Double Speed PCM. Values: 32X and 64X.3264
Quadruple Speed PCM. Values: 16X and 32X.1632
PROTECTION CIRCUITRY
Thermal shutdown temperature 140 °C
Thermal shutdown retry1.5s
VBAT undervoltage lockout threshold (UVLO) UVLO is asserted 4 V
VBAT overvoltage lockout threshold (OVLO) OVLO is asserted 18 V
AMPLIFIER PERFORMANCE
POUT Maximum Continuous Output Power 0.1% THD+N RL = 8 Ω + 33 µH, THD+N = 0.1 %, fin = 1 kHz, VBAT = 8.4 V 3.7W
RL = 4 Ω + 33 µH, THD+N = 0.1 %, fin = 1 kHz, VBAT = 8.4 V 6.6
RL = 8 Ω + 33 µH, THD+N = 0.1 %, fin = 1 kHz, VBAT = 12.6 V 8.5
RL = 4 Ω + 33 µH, THD+N = 0.1 %, fin = 1 kHz, VBAT = 12.6 V 14.2
Maximum Continuous Output Power 1% THD+N RL = 8 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz, VBAT = 8.4 V4
RL = 4 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz, VBAT = 8.4 V7.1
RL = 8 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz, VBAT = 12.6 V9.1
RL = 4 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz, VBAT = 12.6 V15.4
System efficiency at POUT = 1 W RL = 8 Ω + 33 µH, fin = 1 kHz, VBAT = 8.4 V 89 %
RL = 4 Ω + 33 µH, fin = 1 kHz, VBAT = 8.4 V 84 %
RL = 8 Ω + 33 µH, fin = 1 kHz, VBAT = 12.6 V 87.5 %
RL = 4 Ω + 33 µH, fin = 1 kHz, VBAT = 12.6 V 82.7 %
System efficiency at 0.1% THD+N power level RL = 8 Ω + 33 µH, POUT = 3.7W, fin = 1 kHz, VBAT = 8.4 V 92 %
RL = 4 Ω + 33 µH, POUT = 6.6 W, fin = 1 kHz, VBAT = 8.4 V 87 %
RL = 8 Ω + 33 µH, POUT = 8.5 W, fin = 1 kHz, VBAT = 12.6 V 92 %
RL = 4 Ω + 33 µH, POUT = 14.2 W, fin = 1 kHz, VBAT = 12.6 V 86 %
THD+N Total harmonic distortion + noise POUT = 1 W, RL = 8 Ω + 33 µH, fin = 20 Hz - 20 kHz, VBAT = 8.4 V 0.01 %
POUT = 1 W, RL = 4 Ω + 33 µH, fin = 20 Hz - 20 kHz, VBAT = 8.4 V 0.01 %
POUT = 1 W, RL = 8 Ω + 33 µH, fin = 20 Hz - 20 kHz, VBAT = 12.6 V 0.01 %
POUT = 1 W, RL = 4 Ω + 33 µH, fin = 20 Hz - 20 kHz, VBAT = 12.6 V 0.01 %
VN Idle channel noise A-Weighted, 20 Hz - 20 kHz, DAC Modulator Running31µV
VBAT = 8.4 V32
VBAT = 12.6 V36
FPWM Class-D PWM switching frequencyAverage frequency in Spread Spectrum Mode, CLASSD_SYNC=0384kHz
Fixed Frequency Mode, CLASSD_SYNC=0345.6384422.4
Fixed Frequency Mode, CLASSD_SYNC=1, fs = 44.1, 88.2, 174.6 kHz44.1·8
Fixed Frequency Mode, CLASSD_SYNC=1, fs = 48, 96, 192 kHz48·8
VOS Output offset voltage -1 1mV
DNR Dynamic range A-Weighted, -60 dBFS Method 108dB
SNR Signal to noise ratio A-Weighted, Referenced to 1 % THD+N Output Level 108dB
KCP Click and pop performance Into and out of Mute, Shutdown, Power Up, Power Down and audio clocks starting and stopping. A-weighted 5mV
Programmable output level range 12.5 21dBV
Programmable output level step size 0.5dB
AVERRORAmplifier gain errorPOUT=1W ±0.1 dB
ARIPPLEFrequency response passband ripple20 Hz - 20 kHz ±0.1dB
Mute attenuation Device in Shutdown or Muted in Normal Operation 110dB
Output short circuit limit VBAT = 12.6 V, Output to Output, Output to GND or Output to VBAT Short 6 A
RDS(ON)FETPower stage on-resistance (high-side + low-side + sense resistor) TA = 25 °C 510
VBAT power-supply rejection ratio VBAT = 12.6 V + 200 mVpp, fripple = 217 Hz 105dB
VBAT = 12.6 V + 200 mVpp, fripple = 20 kHz 86
AVDD power-supply rejection ratio AVDD = 1.8 V + 200 mVpp, fripple = 217 Hz 95dB
AVDD = 1.8 V + 200 mVpp, fripple = 20 kHz 88
Turn on time from release of SW shutdown No Volume Ramping 1.2ms
Volume Ramping 5.3
Turn off time from assertion of SW shutdown to amp Hi-Z No Volume Ramping 0.3ms
Volume Ramping 4.7
PCM PLAYBACK CHARACTERISTICS
Playback latency from latched input sample to speaker terminals Single Speed, I2S/TDM 3.5samples
Double Speed, I2S/TDM 3.5
Quadruple Speed, I2S/TDM 3.5
Playback –0.1 dB bandwidth Single Speed, I2S/TDM 23.06kHz
Double Speed, I2S/TDM21.79
Quadruple Speed, I2S/TDM 21.69
Playback –3 dB bandwidth Single Speed, I2S/TDM 24kHz
Double Speed, I2S/TDM23
Quadruple Speed, I2S/TDM27.26
PDM PLAYBACK CHARACTERISTICS
Playback latency from latched data bit to speaker terminals Single Rate PDM, PDMD input7.07µs
Double Rate PDM, PDMD input5.02
Playback –0.1 dB bandwidth Single Rate PDM, PDMD input41.5kHz
Double Rate PDM, PDMD input88
Playback –3 dB bandwidth Single Rate PDM, PDMD input77.5kHz
Double Rate PDM, PDMD input143
SPEAKER CURRENT SENSE
DNR Dynamic range Un-Weighted, Relative to 0 dBFS 69dB
THD+N Total harmonic distortion + noise RL = 8 Ω + 33 µH, fin = 1 kHz, POUT = 5 W –60dB
RL = 4 Ω + 33 µH, fin = 1 kHz, POUT = 7.5 W –60
Full-scale input current 3.75A
Current-sense accuracy RL = 8 Ω + 33 µH, IOUT = 354 mARMS (POUT = 1 W) ±1 %
Current-sense gain error over temperature–20°C to 70°C, POUT = 1 W ±0.75%
Current-sense gain error over output power 50 mW to 0.1 % THD+N level, fin = 1 kHz, 4 Ω, using a 40Hz-34dB pilot tone ±0.75%
Current-sense frequency response Max deviation above and below passband gain ±0.2dB
SPEAKER VOLTAGE SENSE
DNR Dynamic range Un-Weighted, Relative 0 dBFS 69dB
THD+N Total harmonic distortion + noise RL = 8 Ω + 33 µH, fin = 1 kHz, POUT = 5 W –60dB
RL = 4 Ω + 33 µH, fin = 1 kHz, POUT = 7.5 W –60
Full-scale input voltage 14VPK
Voltage-sense accuracy RL = 8 Ω + 33 µH, IOUT = 354 mARMS (POUT = 1 W) ±1%
Voltage-sense gain error over temperature–20°C to 70°C, POUT = 1 W ±0.75%
Voltage-sense gain error over output power 50 mW to 0.1 % THD+N level, fin = 1 kHz, 4 Ω, using a 40Hz-34dB pilot tone ±0.75%
Voltage-sense frequency response Max deviation above and below passband gain ±0.2dB
SPEAKER VOLTAGE/CURRENT SENSE RATIO
Gain ratio error over output power 50 mW to 0.1 % THD+N level, fin = 1 kHz, 4 Ω, using a 40Hz-34dB pilot tone ±0.75%
Gain ratio error over temperature–20°C to 70°C ±0.5%
TYPICAL CURRENT CONSUMPTION
Current consumption in hardware shutdown SDZ = 0, VBAT 0.1µA
SDZ = 0, AVDD 1
SDZ = 0, IOVDD 0.1
Current consumption in software shutdown All Clocks Stopped, VBAT 10µA
All Clocks Stopped, AVDD 10
All Clocks Stopped, IOVDD 1
Current consumption during active operation with IV sense disabled fs = 48 kHz, VBAT 3.1mA
fs = 48 kHz, AVDD10
fs = 48 kHz, IOVDD 0.1
Current consumption during active operation with IV sense enabled fs = 48 kHz, VBAT 3.1mA
fs = 48 kHz, AVDD 12.5
fs = 48 kHz, IOVDD 0.1
PEAK VOLTAGE LIMITER
Limiter maximum threshold 214.7V
Limiter minimum threshold 2 14.7V
Limiter inflection point 2 14.7V
Limiter VBAT tracking slope 1 4V/V
Limiter max attenuation 1 16.5dB
Limiter latency Time from VBAT dipping below threshold to initial gain reduction 23µs
Limiter attack rate 5640µs/step
Limiter attack step size 0.25 2dB/step
Limiter hold time 0 1000ms
Limiter release rate 10 1500ms/step
Limiter release step size 0.25 2dB/step
BROWN OUT PREVENTION LIMITER
Brownout prevention threshold 4.5 10.875V
Brownout prevention threshold step size25mV
Brownout prevention threshold toleranceMeasured at VBAT of 5V and 10V±25mV
Brownout prevention latency Time from VBAT dipping below threshold to initial gain reduction 20µs
Brownout prevention attack rate 5640µs/step
Brownout prevention attack step size 0.5 2dB/step
Brownout prevention hold time 0 1000ms
Brownout prevention release rate 10 1500ms/step
Brownout prevention release step size 0.25 2dB/step

I2C Timing Requirements

TA = 25 °C, AVDD = IOVDD = 1.8 V (unless otherwise noted)
MINNOMMAXUNIT
Standard-Mode
fSCL SCL clock frequency0100kHz
tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated.4μs
tLOW LOW period of the SCL clock 4.7μs
tHIGH HIGH period of the SCL clock4μs
tSU;STA Setup time for a repeated START condition 4.7μs
tHD;DAT Data hold time: For I2C bus devices 03.45μs
tSU;DAT Data set-up time250ns
tr SDA and SCL rise time1000ns
tf SDA and SCL fall time300ns
tSU;STO Set-up time for STOP condition4μs
tBUF Bus free time between a STOP and START condition4.7μs
Cb Capacitive load for each bus line 400pF
Fast-Mode
fSCL SCL clock frequency0400kHz
tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated.0.6μs
tLOW LOW period of the SCL clock 1.3μs
tHIGH HIGH period of the SCL clock0.6μs
tSU;STA Setup time for a repeated START condition 40.6μs
tHD;DAT Data hold time: For I2C bus devices 00.9μs
tSU;DAT Data set-up time100ns
tr SDA and SCL rise time20 + 0.1 × Cb300ns
tf SDA and SCL fall time20 + 0.1 × Cb300ns
tSU;STO Set-up time for STOP condition0.26μs
tBUF Bus free time between a STOP and START condition1.3μs
Cb Capacitive load for each bus line 400pF
Fast-Mode Plus
fSCL SCL clock frequency01000kHz
tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated.0.26μs
tLOW LOW period of the SCL clock 0.5μs
tHIGH HIGH period of the SCL clock0.26μs
tSU;STA Setup time for a repeated START condition 0.26μs
tHD;DAT Data hold time: For I2C bus devices 0μs
tSU;DAT Data set-up time50ns
tr SDA and SCL Rise Time120ns
tf SDA and SCL Fall Time120ns
tSU;STO Set-up time for STOP conditionμs
tBUF Bus free time between a STOP and START condition0.5μs
Cb Capacitive load for each bus line 550pF

TDM Port Timing Requirements

TA = 25 °C, AVDD = IOVDD = 1.8 V, 20 pF load on all outputs (unless otherwise noted)
MINNOMMAXUNIT
tH(SBCLK) SBCLK high period 40ns
tL(SBCLK) SBCLK low period 40ns
tSU(FSYNC) FSYNC setup time 8ns
tHLD(FSYNC) FSYNC hold time 8ns
tSU(FSYNC) SDIN setup time 8ns
tHLD(SDIN) SDIN hold time 8ns
td(DO-FSYNC) FSYNC to SDOUT delay (tx_offset = 0 only) 50% of FSYNC to 50% of SDOUT 35ns
td(DO-SBCLK) SBCLK to SDOUT delay 50% of FSYNC to 50% of SDOUT 35ns
tr(SBCLK) SBCLK rise time 10 % - 90 % Rise Time 8ns
tf(SBCLK) SBCLK fall time 90 % - 10 % Fall Time 8ns

PDM Port Timing Requirements

TA = 25 °C, AVDD = IOVDD = 1.8 V, 20 pF load on all outputs (unless otherwise noted)
MINNOMMAXUNIT
tSU(PDM) PDM IN setup time 20ns
tHLD(PDM) PDM IN hold time 3ns
tr(PDM) PDM IN rise time 10 % - 90 % Rise Time 4ns
tf(PDM) PDM IN fall time 90 % - 10 % Fall Time 4ns
TAS2770 tas5770l_i2c_timing.gif Figure 1. I2C Timing Diagram
TAS2770 tas5770l_tdm_timing.gif Figure 2. TDM Timing Diagram
TAS2770 tas5770l_pdm_timing.gif Figure 3. PDM Timing Diagram

Typical Characteristics

At TA = 25°C, fSPK_AMP = 384 kHz, input signal is 1 kHz Sine, unless otherwise noted. Filter used for Load Resistance is 30 µH, unless otherwise noted.
TAS2770 D001_SLASEM6.gif
RL = 4 Ω FIN = 1 kHz
Figure 4. THD+N vs Output Power
TAS2770 D003_SLASEM6.gif
RL = 4 Ω FIN = 6.667 kHz
Figure 6. THD+N vs Output Power
TAS2770 D005_SLASEM6.gif
FIN = 20 Hz – 20 kHz POUT = 0.1 W RL = 4 Ω + 30 µH
Figure 8. THD+N vs Frequency
TAS2770 D007_SLASEM6.gif
FIN = 20 Hz – 20 kHz POUT = 5 W RL = 4 Ω + 30 µH
Figure 10. THD+N vs Frequency
TAS2770 D009_SLASEM6.gif
VBAT = 4.5 V – 16 V
Figure 12. Idle Channel Noise (A-Weighted) vs VBAT
TAS2770 D011_SLASEM6.gif
RL = 4 Ω
Figure 14. Max Output Power vs THD+N
TAS2770 D013_SLASEM6.gif
RL = 4 Ω FIN = 1 kHz
Figure 16. Efficiency vs Output Power
TAS2770 D015_SLASEM6.gif
Figure 18. VDD PSRR vs Frequency
TAS2770 D017_SLASEM6.gif
VBAT = 4.5 V – 16 V
Figure 20. VBAT Idle Current vs VBAT
TAS2770 D019_SLASEM6.gif
RL = 4 Ω FIN = 1 kHz
Figure 22. ISENSE THD+N vs Output Power
TAS2770 D021_SLASEM6.gif
RL = 4 Ω Pilot tone = 40 Hz, 34 dB
Figure 24. ISENSE Gain Linearity vs Output Power
TAS2770 D024_SLASEM6.gif
FIN = 20 Hz – 20 kHz POUT = 1 W
Figure 26. ISENSE THD+N vs Frequency
TAS2770 D026_SLASEM6.gif
RL = 8 Ω
Figure 28. VSENSE THD+N vs Output Power
TAS2770 D028_SLASEM6.gif
FIN = 20 Hz – 20 kHz POUT = 1 W
Figure 30. VSENSE THD+N vs Frequency
TAS2770 D030_SLASEM6.gif
RL = 4 Ω + 30 µH Pilot tone = 40 Hz, 34 dB
Figure 32. V/ISENSE Gain Linearity vs Output Power
TAS2770 D032_SLASEM6.gif
TA = –20°C – 70ºC Pilot tone = 40 Hz, 34 dB
Figure 34. VSENSE Gain Deviation vs Temperature
TAS2770 D002_SLASEM6.gif
RL = 8 Ω FS = 1 kHz FIN = 1 kHz
Figure 5. THD+N vs Output Power
TAS2770 D004_SLASEM6.gif
RL = 8 Ω FIN = 6.667 kHz
Figure 7. THD+N vs Output Power
TAS2770 D006_SLASEM6.gif
FIN = 20 Hz – 20 kHz POUT = 1 W RL = 4 Ω + 30 µH
Figure 9. THD+N vs Frequency
TAS2770 D008_SLASEM6.gif
FIN = 20 Hz – 20 kHz POUT = 1 W RL = 8 Ω + 30 µH
Figure 11. THD+N vs Frequency
TAS2770 D010_SLASEM6.gif
FS = 48 kHz POUT = 1 W
Figure 13. Amplitude vs Frequency
TAS2770 D012_SLASEM6.gif
RL = 8 Ω
Figure 15. Max Output Power vs THD+N
TAS2770 D014_SLASEM6.gif
RL = 8 Ω FIN = 1 kHz
Figure 17. Efficiency vs Output Power
TAS2770 D016_SLASEM6.gif
Figure 19. VBAT PSRR vs Frequency
TAS2770 D018_SLASEM6.gif
AVDD = 1.65 V – 1.95 V IV Sense Enabled
Figure 21. AVDD Idle Current vs AVDD
TAS2770 D020_SLASEM6.gif
RL = 8 Ω FIN = 1 kHz
Figure 23. ISENSE THD+N vs Output Power
TAS2770 D023_SLASEM6.gif
FIN = 20 Hz – 20 kHzPOUT = 1 W
Figure 25. ISENSE THD+N vs Frequency
TAS2770 D025_SLASEM6.gif
RL = 4 Ω
Figure 27. VSENSE THD+N vs Output Power
TAS2770 D027_SLASEM6.gif
RL = 4 Ω Pilot tone = 40 Hz, 34 dB
Figure 29. Output Power vs VSENSE Linearity
TAS2770 D029_SLASEM6.gif
FIN = 20 Hz – 20 kHz POUT = 1 W
Figure 31. VSENSE THD+N vs Frequency
TAS2770 D031_SLASEM6.gif
TA = –20°C – 70ºC Pilot tone = 40 Hz, 34 dB
Figure 33. ISENSE Gain Deviation vs Temperature
TAS2770 D033_SLASEM6.gif
TA = –20°C – 70ºC Pilot tone = 40 Hz, 34 dB
Figure 35. V/ISENSE Gain Deviation vs Temperature