SLOS870B September 2016  – October 2017 TAS6424-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5Electrical Characteristics
    6. 7.6Timing Requirements
    7. 7.7Typical Characteristics
  8. Parameter measurement Information
  9. Detailed description
    1. 9.1Overview
    2. 9.2Functional Block Diagram
    3. 9.3Feature Description
      1. 9.3.1 Serial Audio Port
        1. I2S Mode
        2. Timing
        3. Timing
        4. Mode
        5. Clock Rates
        6. Error Handling
      2. 9.3.2 High-Pass Filter
      3. 9.3.3 Volume Control and Gain
      4. 9.3.4 High-Frequency Pulse-Width Modulator (PWM)
      5. 9.3.5 Gate Drive
      6. 9.3.6 Power FETs
      7. 9.3.7 Load Diagnostics
        1. Load Diagnostics
        2. Output Diagnostics
        3. Load Diagnostics
      8. 9.3.8 Protection and Monitoring
        1. Limit (ILIMIT)
        2. Shutdown (ISD)
        3. Detect
        4. Detect
        5. Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)
        6. Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]
        7. (UV) and Power-On-Reset (POR)
        8. (OV) and Load Dump
      9. 9.3.9 Power Supply
        1. Power-Supply Sequence
        2. Power-Supply Sequence
      10. 9.3.10Hardware Control Pins
    4. 9.4Device Functional Modes
      1. 9.4.1Operating Modes and Faults
    5. 9.5Programming
      1. 9.5.1I2C Serial Communication Bus
      2. 9.5.2I2C Bus Protocol
      3. 9.5.3Random Write
      4. 9.5.4Sequential Write
      5. 9.5.5Random Read
      6. 9.5.6Sequential Read
    6. 9.6Register Maps
      1. 9.6.1 Mode Control Register (address = 0x00) [default = 0x00]
      2. 9.6.2 Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
      3. 9.6.3 Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
      4. 9.6.4 SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]
      5. 9.6.5 Channel State Control Register (address = 0x04) [default = 0x55]
      6. 9.6.6 Channel 1 Through 4 Volume Control Registers (address = 0x05-0x088) [default = 0xCF]
      7. 9.6.7 DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
      8. 9.6.8 DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
      9. 9.6.9 DC Load Diagnostic Control 3 Register (address = 0x0B) [default = 0x11]
      10. 9.6.10DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
      11. 9.6.11DC Load Diagnostic Report 2 Register (address = 0x0D) [default = 0x00]
      12. 9.6.12DC Load Diagnostics Report 3—Line Output—Register (address = 0x0E) [default = 0x00]
      13. 9.6.13Channel State Reporting Register (address = 0x0F) [default = 0x55]
      14. 9.6.14Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]
      15. 9.6.15Global Faults 1 Register (address = 0x11) [default = 0x00]
      16. 9.6.16Global Faults 2 Register (address = 0x12) [default = 0x00]
      17. 9.6.17Warnings Register (address = 0x13) [default = 0x20]
      18. 9.6.18Pin Control Register (address = 0x14) [default = 0xFF]
      19. 9.6.19AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
      20. 9.6.20AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
      21. 9.6.21AC Load Diagnostic Impedance Report Ch1 through CH4 Registers (address = 0x17-0x1A) [default = 0x00]
      22. 9.6.22AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]
      23. 9.6.23AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]
      24. 9.6.24AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]
      25. 9.6.25AC Load Diagnostic STI Report Low Register (address = 0x1C) [default = 0x00]
      26. 9.6.26Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
      27. 9.6.27Clip Control Register (address = 0x22) [default = 0x01]
      28. 9.6.28Clip Window Register (address = 0x23) [default = 0x14]
      29. 9.6.29Clip Warning Register (address = 0x24) [default = 0x00]
      30. 9.6.30ILIMIT Status Register (address = 0x25) [default = 0x00]
      31. 9.6.31Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]
  10. 10Application and Implementation
    1. 10.1Application Information
      1. 10.1.1AM-Radio Band Avoidance
      2. 10.1.2Parallel BTL Operation (PBTL)
      3. 10.1.3Demodulation Filter Design
      4. 10.1.4Line Driver Applications
    2. 10.2Typical Applications
      1. 10.2.1BTL Application
        1. Requirements
        2. Supplies
        4. Design Procedure
          1. Design
          2. Input and the Serial Audio Port
          3. Capacitors
          4. Reconstruction Filter
        5. Curves
      2. 10.2.2PBTL Application
        1. Requirements
          1. Design Procedure
        2. Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1Layout Guidelines
      1. 12.1.1Electrical Connection of Thermal pad and Heat Sink
      2. 12.1.2EMI Considerations
      3. 12.1.3General Guidelines
    2. 12.2Layout Example
    3. 12.3Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1Documentation Support
      1. 13.1.1Related Documentation
    2. 13.2Receiving Notification of Documentation Updates
    3. 13.3Community Resources
    4. 13.4Trademarks
    5. 13.5Electrostatic Discharge Caution
    6. 13.6Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The TAS6424-Q1 is a four-channel class-D digital-input audio-amplifier design for use in automotive head units and external amplifier modules. The TAS6424-Q1 incorporates the necessary functionality to perform in demanding OEM applications.

AM-Radio Band Avoidance

AM-radio frequency interference can be avoided by setting the switching frequency of the device above the AM band. The switching frequency options available are 38 fs, 44 fs, and 48 fs. If the switch frequency cannot be set above the AM band, then use the two options of 8 fs and 10 fs. These options should be changed to avoid AM active channels.

Parallel BTL Operation (PBTL)

The device can drive more current-paralleling BTL channels on the load side of the LC output filter. For parallel operation, the parallel BTL mode, PBTL, must be used and the paralleled channels must have the same state in the state control register. If the two states are not aligned the device reports a fault condition.

To set the requested channels to PBTL mode the device must be in standby mode for the commands to take effect.

A load diagnostic is supported for PBTL channels. Paralleling on the device side of the LC output filter is not supported.

Demodulation Filter Design

The amplifier outputs are driven by high-current LDMOS transistors in an H-bridge configuration. These transistors are either fully off or fully on. The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the audio signal. An LC demodulation filter is used to recover the audio signal. The filter attenuates the high-frequency components of the output signals that are out of the audio band. The design of the demodulation filter significantly affects the audio performance of the power amplifier. Therefore, to meet the system THD+N requirements, the selection of the inductors used in the output filter should be carefully considered.

Line Driver Applications

In many automotive audio applications, the same head unit must drive either a speaker (with several ohms of impedance) or an external amplifier input (with several kiloohms of impedance). The design is capable of supporting both applications and has special line-drive gain and diagnostics. Coupled with the high switching frequency, the device is well suited for this type of application. Set the desired channel in line driver mode through I2C register 0x00, the externally connected amplifier must have a differential impedance from 600 Ω to 4.7 kΩ for the DC line diagnostic to detect the connected external amplifier. Figure 78 shows the recommended external amplifier input configuration.

TAS6424-Q1 Line_Out_SLOS870.gif Figure 78. External Amplifier Input Configuration for Line Driver

Typical Applications

BTL Application

Figure 79 shows the schematic of a typical 4-channel solution for a head-unit application.

TAS6424-Q1 typ_app_slos870.gif Figure 79. Typical 4-Channel BTL Application Schematic

Design Requirements

Use the following requirements for this design:

  • This head-unit example is focused on the smallest solution size for 4 × 50-W output power into 2 Ω with a battery supply of 14.4 V.
  • The switching frequency is set above the AM-band with 44 times the input sample rate of 48 kHz which results in a frequency of 2.11 MHz.
  • The selection of a 2.11-MHz switch frequency enables the use of a small output inductor value of 3.3 µH which leads to a very small solution size.

Power Supplies

The TAS6424-Q1 requires three power supplies. The PVDD supply is the high-current supply in the recommended supply range. The VBAT supply is lower current supply that must be in the recommended supply range. The PVDD and VBAT pins can be connected to the same supply if the recommended supply range for VBAT is maintained. The VDD supply is the 3.3-Vdc logic supply and must be maintained in the tolerance as shown in the Recommended Operating Conditions table.


All communications to the TAS6424-Q1 are through the I2C protocol. A system controller can communicate with the device through the SDA pins and SCL pins. The TAS6424-Q1 is an I2C slave device and requires a master. The device cannot generate an I2C clock or initiate a transaction. The maximum clock speed accepted by the device is 400 kHz. If multiple TAS6424-Q1 devices are on the same I2C bus, the I2C address must be different for each device. Up to four TAS6424-Q1 devices can be on the same I2C bus.

The I2C bus is shared internally.


Complete any internal operations, such as load diagnostics, before reading the registers for the results.

Detailed Design Procedure

Hardware Design

Use the following procedure for the hardware design:

  • Determine the input format. The input format can be either I2S or TDM mode. The mode determines the correct pin connections and the I2C register settings.
  • Determine the power output that is required into the load. The power requirement determines the required power-supply voltage and current. The output reconstruction-filter components that are required are also driven by the output power.
  • With the requirements, adjust the typical application schematic in Figure 79 for the input connections.

Digital Input and the Serial Audio Port

The TAS6424-Q1 device supports four different digital input formats which are: I2S, Right Justified, Left Justified, and TDM mode. Depending on the format, the device can support 16-, 18-, 20-, 24-, and 32-bit data. The supported frequencies are 96 kHz, 48 kHz, and 44.1 kHz. Please see Table 13 for the I2C register, SAP Control, for the complete matrix to set up the serial audio port.


Bits 3, 4, and 5 in this register are ignored in all input formats except for TDM. Setting up all the control registers to the system requirements should be done before the device is placed in Mute mode or Play mode. After the registers are setup, use bit 7 in register 0x21 to clear any faults. Then read the fault registers to make sure no faults are present. When no faults are present, use register 0x04 to place the device properly into play mode.

Bootstrap Capacitors

The bootstrap capacitors provide the gate-drive voltage of the upper N-channel FET. These capacitors must be sized appropriately for the system specification. A special condition can occur where the bootstrap may sag if the capacitor is not sized accordingly. The special condition is just below clipping where the PWM is slightly less than 100% duty cycle with sustained low-frequency signals. Changing the bootstrap capacitor value to 2.2 µF for driving subwoofers that require frequencies below 30 Hz may be necessary.

Output Reconstruction Filter

The output FETs drive the amplifier outputs in an H-Bridge configuration. These transistors are either fully off or fully on. The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the audio signal. The amplifier outputs require a reconstruction filter that comprises a series inductor and a capacitor to ground on each output, generally called an LC filter. The LC filter attenuates the PWM frequency and reduces electromagnetic emissions, allowing the reconstructed audio signal to pass to the speakers. refer to the Class-D LC Filter Design, (SLOA119) for a detailed description of proper component description and design of the LC filter based upon the specified load and frequency response. The recommended low-pass cutoff frequency of the LC filter is dependent on the selected switching frequency. The low-pass cutoff frequency can be as high as 100 kHz for a PWM frequency of 2.1 MHz. At a PWM frequency of 384 kHz the low-pass cutoff frequency should be less than 40 kHz. Certain specifications must be understood for a proper inductor. The inductance value is given at zero current, but the TAS6424-Q1 device will have current. Use the inductance versus current curve for the inductor to make sure the inductance does not drop below 2 µH (for fSW = 2.1 MHz) at the maximum current provided by the system design. The DCR of the inductor directly affects the output power of the system design. The lower the DCR, the more power is provided to the speakers. The typical inductor DCR for a 4-Ω system is 40 to 50 mΩ and for a 2-Ω system is 20 to 25 mΩ.

Application Curves

TAS6424-Q1 D010_SLOS870.gif
1 kHzPVDD = 14.4 V
Figure 80. THD vs Output Power, 4R
TAS6424-Q1 D006_SLOS870.gif
1 WPVDD = 14.4 V
Figure 81. THD vs Frequency

PBTL Application

Figure 82 shows a schematic of a typical 2-channel solution for a head unit or external amplifier application where high power into 2 Ω is required.

To operate in PBTL mode the output stage must be paralleled according to the schematic in Figure 82. The device can operate in a mix of PBTL and BTL mode. This application can be set up for 3 channels, with one channel in PBTL mode and two channels in BTL mode. The device does not support a parallel configuration all four channels for a one-channel amplifier.

TAS6424-Q1 PBTL_app_slos870.gif Figure 82. 2-Channel PBTL Application Schematic

Design Requirements

Use the following requirements for this design:

  • This head-unit example is focused on the smallest solution size for 2 times 50-W output power into 2 Ω with a battery supply of 14.4 V
  • The switching frequency is set above the AM-band with 44 times the input sample rate of 48 kHz which results in a frequency of 2.11 MHz.
  • The selection of a 2.11-MHz switch frequency enables the use of a small output inductor value of 3.3 µH which leads to a very small solution size.

Detailed Design Procedure

As a starting point, refer to the Detailed Design Procedure section for the BTL application. PBTL mode requires schematic changes in the output stage as shown in Figure 82. The other required changes include setting up the I2C registers correctly (see Table 13) and selecting which frame or channel to use on each output. Bit 6 in register 0x21 controls the frame selection.

Application Curves

TAS6424-Q1 D033_SLOS870.gif
1 kHzPVDD = 14.4 V
Figure 83. THD vs Output Power, 2R
TAS6424-Q1 D031_SLOS870.gif
1 WPVDD = 14.4 V
Figure 84. Frequency Response