SLOS870B September 2016  – October 2017 TAS6424-Q1

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5Electrical Characteristics
    6. 7.6Timing Requirements
    7. 7.7Typical Characteristics
  8. Parameter measurement Information
  9. Detailed description
    1. 9.1Overview
    2. 9.2Functional Block Diagram
    3. 9.3Feature Description
      1. 9.3.1 Serial Audio Port
        1. 9.3.1.1 I2S Mode
        2. 9.3.1.2Left-Justified Timing
        3. 9.3.1.3Right-Justified Timing
        4. 9.3.1.4TDM Mode
        5. 9.3.1.5Supported Clock Rates
        6. 9.3.1.6Audio-Clock Error Handling
      2. 9.3.2 High-Pass Filter
      3. 9.3.3 Volume Control and Gain
      4. 9.3.4 High-Frequency Pulse-Width Modulator (PWM)
      5. 9.3.5 Gate Drive
      6. 9.3.6 Power FETs
      7. 9.3.7 Load Diagnostics
        1. 9.3.7.1DC Load Diagnostics
        2. 9.3.7.2Line Output Diagnostics
        3. 9.3.7.3AC Load Diagnostics
      8. 9.3.8 Protection and Monitoring
        1. 9.3.8.1Overcurrent Limit (ILIMIT)
        2. 9.3.8.2Overcurrent Shutdown (ISD)
        3. 9.3.8.3DC Detect
        4. 9.3.8.4Clip Detect
        5. 9.3.8.5Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)
        6. 9.3.8.6Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]
        7. 9.3.8.7Undervoltage (UV) and Power-On-Reset (POR)
        8. 9.3.8.8Overvoltage (OV) and Load Dump
      9. 9.3.9 Power Supply
        1. 9.3.9.1Vehicle-Battery Power-Supply Sequence
        2. 9.3.9.2Boosted Power-Supply Sequence
      10. 9.3.10Hardware Control Pins
        1. 9.3.10.1FAULT
        2. 9.3.10.2WARN
        3. 9.3.10.3MUTE
        4. 9.3.10.4STANDBY
    4. 9.4Device Functional Modes
      1. 9.4.1Operating Modes and Faults
    5. 9.5Programming
      1. 9.5.1I2C Serial Communication Bus
      2. 9.5.2I2C Bus Protocol
      3. 9.5.3Random Write
      4. 9.5.4Sequential Write
      5. 9.5.5Random Read
      6. 9.5.6Sequential Read
    6. 9.6Register Maps
      1. 9.6.1 Mode Control Register (address = 0x00) [default = 0x00]
      2. 9.6.2 Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
      3. 9.6.3 Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
      4. 9.6.4 SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]
      5. 9.6.5 Channel State Control Register (address = 0x04) [default = 0x55]
      6. 9.6.6 Channel 1 Through 4 Volume Control Registers (address = 0x05-0x088) [default = 0xCF]
      7. 9.6.7 DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
      8. 9.6.8 DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
      9. 9.6.9 DC Load Diagnostic Control 3 Register (address = 0x0B) [default = 0x11]
      10. 9.6.10DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
      11. 9.6.11DC Load Diagnostic Report 2 Register (address = 0x0D) [default = 0x00]
      12. 9.6.12DC Load Diagnostics Report 3—Line Output—Register (address = 0x0E) [default = 0x00]
      13. 9.6.13Channel State Reporting Register (address = 0x0F) [default = 0x55]
      14. 9.6.14Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]
      15. 9.6.15Global Faults 1 Register (address = 0x11) [default = 0x00]
      16. 9.6.16Global Faults 2 Register (address = 0x12) [default = 0x00]
      17. 9.6.17Warnings Register (address = 0x13) [default = 0x20]
      18. 9.6.18Pin Control Register (address = 0x14) [default = 0xFF]
      19. 9.6.19AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
      20. 9.6.20AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
      21. 9.6.21AC Load Diagnostic Impedance Report Ch1 through CH4 Registers (address = 0x17-0x1A) [default = 0x00]
      22. 9.6.22AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]
      23. 9.6.23AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]
      24. 9.6.24AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]
      25. 9.6.25AC Load Diagnostic STI Report Low Register (address = 0x1C) [default = 0x00]
      26. 9.6.26Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
      27. 9.6.27Clip Control Register (address = 0x22) [default = 0x01]
      28. 9.6.28Clip Window Register (address = 0x23) [default = 0x14]
      29. 9.6.29Clip Warning Register (address = 0x24) [default = 0x00]
      30. 9.6.30ILIMIT Status Register (address = 0x25) [default = 0x00]
      31. 9.6.31Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]
  10. 10Application and Implementation
    1. 10.1Application Information
      1. 10.1.1AM-Radio Band Avoidance
      2. 10.1.2Parallel BTL Operation (PBTL)
      3. 10.1.3Demodulation Filter Design
      4. 10.1.4Line Driver Applications
    2. 10.2Typical Applications
      1. 10.2.1BTL Application
        1. 10.2.1.1Design Requirements
        2. 10.2.1.2Power Supplies
        3. 10.2.1.3Communication
        4. 10.2.1.4Detailed Design Procedure
          1. 10.2.1.4.1Hardware Design
          2. 10.2.1.4.2Digital Input and the Serial Audio Port
          3. 10.2.1.4.3Bootstrap Capacitors
          4. 10.2.1.4.4Output Reconstruction Filter
        5. 10.2.1.5Application Curves
      2. 10.2.2PBTL Application
        1. 10.2.2.1Design Requirements
          1. 10.2.2.1.1Detailed Design Procedure
        2. 10.2.2.2Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1Layout Guidelines
      1. 12.1.1Electrical Connection of Thermal pad and Heat Sink
      2. 12.1.2EMI Considerations
      3. 12.1.3General Guidelines
    2. 12.2Layout Example
    3. 12.3Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1Documentation Support
      1. 13.1.1Related Documentation
    2. 13.2Receiving Notification of Documentation Updates
    3. 13.3Community Resources
    4. 13.4Trademarks
    5. 13.5Electrostatic Discharge Caution
    6. 13.6Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • DKQ|56
Orderable Information

Detailed description

Overview

The TAS6424-Q1 device is a four-channel digital-input Class-D audio amplifier for use in the automotive environment. The device is designed for vehicle battery operation or boosted voltage systems. The design uses ultra-efficient class-D technology developed by Texas Instruments specifically tailored for the automotive industry. This technology allows for reduced power consumption, reduced PCB area, reduced heat, and reduced peak currents in the electrical system. The device realizes an audio sound-system design with smaller size and lower weight than traditional class-AB solutions.

The core design blocks are as follows:

  • Serial audio port
  • Clock management
  • High-pass filter and volume control
  • Pulse width modulator (PWM) with output stage feedback
  • Gate drive
  • Power FETs
  • Diagnostics
  • Protection
  • Power supply
  • I2C serial communication bus

Functional Block Diagram

TAS6424-Q1 fbd_slos870.gif

Feature Description

Serial Audio Port

The serial audio port (SAP) receives audio in either I2S, left justified, right justified, or TDM formats.

Settings for the serial audio port are programmed in the SAP control register (address 0x03), see the SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04] section.

Figure 35 shows the digital audio data connections for I2S and TDM8 mode for an eight channel system.

TAS6424-Q1 i2S_TDM_slos870.gif Figure 35. Digital-Audio Data Connection

I2S Mode

I2S timing uses the FSYNC pin to define when the data being transmitted is for the left channel and when it is for the right channel. The FSYNC pin is low for the left channel and high for the right channel. The bit clock, SCLK, runs at 32 or 64 × fS and is used to clock in the data. A delay of one bit clock occurs from the time the FSYNC signal changes state to the first bit of data on the data lines. The data is presented in 2s-complement form (MSB-first). The data is valid on the rising edge of the bit clock and is used to clock in the data.

Left-Justified Timing

Left-justified (LJ) timing also uses the FSYNC pin to define when the data being transmitted is for the left channel and when it is for the right channel. The FSYNC pin is high for the left channel and low for the right channel. A bit clock running at 32 or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time FSYNC toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. Digital words can be 16-bits or 24-bits wide and pad any unused trailing data-bit positions in the left-right (L/R) frame with zeros.

Right-Justified Timing

Right-justified (RJ) timing also uses the FSYNC pin to define when the data being transmitted is for the left channel and when it is for the right channel. The FSYNC pin is high for the left channel and low for the right channel. A bit clock running at 32 or 64 × fS is used to clock in the data. The first bit of data appears on the data 8-bit clock periods (for 24-bit data) after the FSYNC pin toggles. In RJ mode the LSB of data is always clocked by the last bit clock before the FSYNC pin transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The device pads the unused leading data-bit positions in the L/R frame with zeros.

TDM Mode

TDM mode supports 4 or 8 channels of audio data. The device can be configured through I2C to use different stereo pairs in the TDM data stream. The TDM mode supports 16-bit, 24-bit, and 32-bit input data lengths.

In TDM mode, the SCLK pin must be 128 or 256, depending on the TDM slot size. In TDM mode SCLK and MCLK can be connected together

In TDM mode, the SDIN1 pin (pin 15) is used for digital audio data. TI recommends to connect the unused SDIN2 pin (pin 16) to ground. Table 1 lists register settings for the TDM channel selection.

Table 1. TDM Channel Selection

REGISTER SETTINGTDM8 CHANNEL SLOT
0x03
BIT 5
0x03
BIT 3
12345678
00CH1CH2CH3CH4
10CH1CH2CH3CH4
01CH3CH4CH1CH2
11CH3CH4CH1CH2

If PBTL mode is programmed for channel 1/2 or channel 3/4 the datasource can be set according to Table 2.

Table 2. TDM Channel Selection in PBTL Mode

REGISTER SETTINGTDM8 CHANNEL SLOT
0x03
BIT 5
0x03
BIT 3
0x21
BIT 6
12345678
000PBTL CH1/2PBTL CH3/4
100PBTL CH1/2PBTL CH3/4
001PBTL CH1/2PBTL CH3/4
101PBTL CH1/2PBTL CH3/4
010PBTL CH3/4PBTL CH1/2
110PBTL CH3/4PBTL CH1/2
011PBTL CH3/4PBTL CH1/2
111PBTL CH3/4PBTL CH1/2

Supported Clock Rates

The device supports MCLK rates of 128 × fS, 256 × fS, or 512 × fS.

The device supports SCLK rates of 32 × fS, 48 × fS or 64 × fS.

The device supports FSYNC rates of 44.1 kHz, 48 kHz, or 96 kHz.

The maximum clock frequency is 25 MHz. Therefore, for a 96-kHz FSYNC rate, the maximum MCLK rate is
256 × fS.

The MCLK clock must not be in phase to sync to SCLK. Duty cycle of 50% is required for 128x FSYNC, for 256x and 512x 50% duty is not required.

Audio-Clock Error Handling

When any kind of clock error, MCLK-FSYNC or SCLK-FSYNC ratio, or clock halt is detected, the device puts all channels into the Hi-Z state. When all audio clocks are within the expected range, the device automatically returns to the state it was in. See the Timing Requirements table for timing requirements.

TAS6424-Q1 td_serial-audio_slos870.gif Figure 36. Serial Audio Timing
TAS6424-Q1 aud_data_format_lj_slos870.gif Figure 37. Left-Justified Audio Data Format
TAS6424-Q1 aud_data_format_i2s_slos870.gif Figure 38. I2S Audio Data Format
TAS6424-Q1 aud_data_format_TDM_slos870.gif Figure 39. TDM Audio Data Format

High-Pass Filter

Direct-current (DC) content in the audio signal can damage speakers. The data path has a high-pass filter to remove any DC from the input signal. The corner frequency is selectable from 4 Hz, 8 Hz, or 15 Hz to 30 Hz with bits 0 through 3 in register 0x26. The default value of –3 dB is approximately 4 Hz for 44.1 kHz or 48 kHz and approximately 8 Hz for 96-kHz sampling rates.

Volume Control and Gain

Each channel has a independent digital-volume control with a range from –100 dB to +24 dB with 0.5-dB steps. The volume control is set through I2C. The gain-ramp rate is programmable through I2C to take one step every 1, 2, 4, or 8 FSYNC cycles.

The peak output-voltage swing is also configurable in the gain control register through I2C. The four gain settings are 7.5 V, 15 V, 21 V, and 29 V. TI recommends selecting the lowest possible for the expected PVDD operation to optimize output noise and dynamic range performance.

High-Frequency Pulse-Width Modulator (PWM)

The PWM converts the PCM input data into a switched signal of varying duty cycle. The PWM modulator is an advanced design with high bandwidth, low noise, low distortion, and excellent stability. The output switching rate is synchronous to the serial audio-clock input and is programmed through I2C to be between 8× and 48× the input-sample rate. The option to switch at high frequency allows the use of smaller and lower cost external filtering components. Table 3 lists the switch frequency options for bits 4 through 6 in the miscellaneous control 2 register (address 0x02).

Table 3. Output Switch Frequency Option

INPUT SAMPLE RATE BIT 6:4 SETTINGS
000001010 to 100101110111
44.1 kHz352.8 kHz441 kHzRESERVED1.68 MHz1.94 MHz2.12 MHz
48 kHz384 kHz480 kHzRESERVED1.82 MHz2.11 MHzNot supported
96 kHz384 kHz480 kHzRESERVED1.82 MHz2.11 MHzNot supported

Gate Drive

The gate driver accepts the low-voltage PWM signal and level shifts it to drive a high-current, full-bridge, power-FET stage. The device uses proprietary techniques to optimize EMI and audio performance.

The gate-driver power-supply voltage, GVDD, is internally generated and a decoupling capacitor is connected at pin 9 and pin 10.

The full H-bridge output stages use only NMOS transistors. Therefore, bootstrap capacitors are required for the proper operation of the high side NMOS transistors. A 1-µF ceramic capacitor of quality X7R or better, rated for at least 16 V, must be connected from each output to the corresponding bootstrap input (see the application circuit diagram in Figure 79). The bootstrap capacitors connected between the BST pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high keeping the high-side MOSFETs turned on.

Power FETs

The BTL output for each channel comprises four N-channel 90-mΩ FETs for high efficiency and maximum power transfer to the load. These FETs are designed to handle the fast switching frequency and large voltage transients during load dump.

Load Diagnostics

The device incorporates both DC-load and AC-load diagnostics which are used to determine the status of the load. The DC diagnostics are turned on by default but if a fast startup without diagnostics is required the DC diagnostics can be bypassed through I2C. The DC diagnostics runs when any channel is directed to leave the Hi-Z state and enter the MUTE or PLAY state. The DC diagnostics can also be enabled manually to run on any or all channels even if the other channels are playing audio. DC Diagnostics can be started from any operating condition but if the channel is in play state then the time to complete the diagnostic is longer because the device must ramp down the audio signal of that channel before transitioning to the Hi-Z state. The DC diagnostics are available as soon as the device supplies are within the recommended operating range. The DC diagnostics do not rely on the audio input clocks to be available to function. DC Diagnostic results are reported for each channel separately through the I2C registers.

DC Load Diagnostics

The DC load diagnostics are used to verify the load connected. The DC diagnostics consists of four tests: short-to-power (S2P), short-to-ground (S2G), open-load (OL), and shorted-load (SL). The S2P and S2G tests trigger if the impedance to GND or a power rail is below that specified in the Specifications section. The diagnostic detects a short to vehicle battery even when the supply is boosted. The SL test has an I2C-configurable threshold depending on the expected load to be connected. Because the speakers connected to each channel might be different, each channel can be assigned a unique threshold value. The OL test reports if the select channel has a load impedance greater than the limits in the Specifications section.

TAS6424-Q1 load_diagnostic_threshold_slos870.gif Figure 40. DC Load Diagnostic Reporting Thresholds

Line Output Diagnostics

The device also includes an optional test to detect a line-output load. A line-output load is a high-impedance load that is above the open-load (OL) threshold such that the DC-load diagnostics report an OL condition. After an OL condition is detected on a channel, if the line output detection bit is also set, the channel checks if a line-output load is present as well. This test is not pop free, so if an external amplifier is connected it should be muted.

AC Load Diagnostics

The AC load diagnostic is used to determine the proper connection of a capacitively coupled speaker or tweeter when used with a passive crossover. The AC load diagnostic is controlled through I2C. The AC diagnostics requires an external input signal and reports the approximate load impedance and phase. The selected signal frequency should create current flow through the desired speaker for proper detection. If multiple channels must be tested, the diagnostics should be run in series. The AC load-diagnostic test procedure is as follows.

For load-impedance detection, use the following test procedure:

  1. Set the channels to be tested into the Hi-Z state.
  2. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 0.
  3. Apply a full-scale input signal from the DSP for the tested channels with the desired frequency (recommended 10 kHz to 20 kHz).
  4. NOTE

    The device ramps the signal up and down automatically to prevent pops and clicks.

  5. Set the device into the AC diagnostic mode (set bits 3:0 in register 0x15 to 1 for CH1 to CH4, set bit 3 in register 0x15 to 1, and set bit 1 in register 0x15 to 1 for PBTL12 and PBTL34).
  6. Read back the AC impedance (register 0x17 through register 0x1A).
  7. When the test is complete the channel reporting register indicates the status change from the AC diagnostic mode to the Hi-Z state. The detected impedance is stored in the appropriate I2C register.

For loopback delay detection, use the following test procedure for either BTL mode or PBTL mode:

  • BTL mode
    1. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 1 to enable AC loopback mode.
    2. Apply a 0-dBFS 19K signal and enable AC load diagnostics. CH1 and CH2 reuse the AC sensing loop of CH1 (set bit 3 in register 0x15 to 1). CH3, CH4 reuse the AC sensing loop of CH3 (set bit 1 in register 0x15 to 1)
    3. Read back the AC_LDG_PHASE1 value (register 0x1B and register 0x1C).
    4. When the test is complete, the channel reporting register indicates the status change from the AC diagnostic mode to the Hi-Z state. The detected impedance is stored in the appropriate I2C register.

  • PBTL mode
    1. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 1 to enable AC loopback mode.
    2. Set the PBTL CH12 and PBTL CH34 bits (bits 5 and 4 in register 0x00) to 0 without toggling SDz pin to enter BTL mode only for load diagnostics.
    3. Apply a 0-dBFS 19K signal and enable AC load diagnostics. For PBTL_12, enable the AC sensing loop of CH1 (set bit 3 in register 0x15 to 1). For PBTL_34, enable the AC sensing loop of CH3 (set bit 1 in register 0x15 to 1).
    4. Read back the AC_LDG_PHASE1 (register 0x1B and register 0x1C).
    5. Set the PBTL CH12 and PBTL CH34 bits (bits 5 and 4 in register 0x00) to 1 to go back to PBTL mode for load diagnostics.

Table 4. AC Impedance Code to Magnitude

SETTINGGAIN AT 19 kHzI(A)MEASUREMENT RANGE (Ω)MAPPING FROM CODE TO MAGNITUDE (Ω/Code)
Gain = 4, I = 10 mA (recommended)4.280.01120.05832
Gain = 4, I = 19 mA4.280.01960.0307
Gain = 1, I = 10 mA (recommended)10.01480.2496
Gain = 1, I = 19 mA10.019240.1314

Protection and Monitoring

Overcurrent Limit (ILIMIT)

The overcurrent limit terminates each PWM pulse to limit the output current flow when the current limit (ILIMIT) is exceeded. Power is limited but operation continues without disruption and prevents undesired shutdown for transient music events. ILIMIT is not reported as a fault condition to either registers or the FAULT pin. Each channel is independently monitored and limited. The two programable levels can be set by bit 4 in the miscellaneous control 1 register (address 0x01).

Overcurrent Shutdown (ISD)

If the output load current reaches ISD, such as an output short to GND, then a peak current limit occurs which shuts down the channel. The time to shutdown the channel varies depending on the severity of the short condition. The affected channel is placed into the Hi-Z state, the fault is reported to the register, and the FAULT pin is asserted. If the diagnostics are enabled then the device automatically starts diagnostics on the channel and, if no load failure is found, the device restarts. If a load fault is found the device continues to rerun the diagnostics once per second. Because this hiccup mode is using the diagnostics, no high current is created. If the diagnostics are disabled the device sets the state for that channel to Hi-Z and requires the MCU to take the appropriate action.

There are two programable levels that can be set by bit 4 in the miscellaneous control 1 register (address 0x01).

DC Detect

This circuit detects a DC offset continuously during normal operation at the output of the amplifier. If the DC offset exceeds the threshold, that channel is placed in the Hi-Z state, the fault is reported to the I2C register, and the FAULT pin is asserted. A register bit can be used to mask reporting to the FAULT pin if needed.

Clip Detect

The clip detect is reported on the WARN pin if 100% duty-cycle PWM if reached for a minimum of 20 cycles. If any channel is clipping, the clipping is reported to the pin. The clip detect is latched and can be cleared by I2C . Masking the clip reporting to the pin is possible through I2C.

Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)

Four overtemperature warning levels are available in the device that can be selected (see the Register Maps section for thresholds). When the junction temperature exceeds the warning level, the WARN pin is asserted unless the mask bit has been set to disable reporting. The device functions until the OTSD value is reached at which point all channels are placed in the Hi-Z state and the FAULT pin is asserted. When the junction temperature returns to normal levels, the device automatically recovers and places all channels into the state indicated by the register settings.

Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]

In addition to the global OTW, each channel also has an individual overtemperature warning and shutdown. If a channel exceeds the OTW(i) threshold, the warning register bit is set as the WARN pin is asserted unless the mask bit has been set to disable reporting. If the channel temperature exceeds the OTSD(i) threshold then that channel goes to the Hi-Z state until the temperature drops below the OTW(i) threshold at which point the channel goes to the state indicated by the state control register.

Undervoltage (UV) and Power-On-Reset (POR)

The undervoltage (UV) protection detects low voltages on the PVDD and VBAT pins. In the event of an UV condition, the FAULT pin is asserted and the I2C register is updated. A power-on reset (POR) on the VDD pin causes the I2C to goes to the high-impedance (Hi-Z) state and all registers are reset to default values. At power-on or after a POR event, the POR warning bit and WARN pin are asserted.

Overvoltage (OV) and Load Dump

The overvoltage (OV) protection detects high voltages on the PVDD pin. If the PVDD pin reaches the OV threshold, the FAULT pin is asserted and the I2C register is updated. The device can withstand 40-V load-dump voltage spikes.

Power Supply

The device has three power supply inputs, VDD, PVDD, and VBAT, which are described as follows:

    VDD This pin is a 3.3-V supply pin that provides power to the low voltage circuitry.
    VBAT This pin is a higher voltage supply that can be connected to the vehicle battery or the regulated voltage rail in a boosted system within the recommended limits. For best performance, this rail should be 10 V or higher. See the Recommended Operating Conditions table for the maximum supply voltage. This supply rail is used for higher voltage analog circuits but not the output FETs.
    PVDD This pin is a high-voltage supply that can either be connected to the vehicle battery or to another voltage rail in a boosted system. The PVDD pin supplies the power to the output FETs and can be within the recommended operating limits, even if that is below the VBAT supply, to allow for dynamic voltage systems.

Several on-chip regulators are included generating the voltages necessary for the internal circuitry. The external pins are provided only for bypass capacitors to filter the supply and should not be used to power other circuits.

The device can withstand fortuitous open ground and power conditions within the absolute maximum ratings for the device. Fortuitous open ground usually occurs when a speaker wire is shorted to ground, allowing for a second ground path through the body diode in the output FETs.

Vehicle-Battery Power-Supply Sequence

The device can accept any sequence of the VBAT, PVDD and VDD supply.

In a typical system, the VBAT and PVDD supplies are both connected to the vehicle battery and power up at the same time. The VDD supply should be applied after the VBAT and PVDD supplies are within the recommended operating range. When removing power from the device, TI recommends to deassert the VDD supply first then the VBAT, PVDD, or both supplies which provides the lowest click and pop performance.

Boosted Power-Supply Sequence

In this case, the VBAT and PVDD inputs are not connected to the same supply.

When powering up, apply the VBAT supply first, the VDD supply second, and the PVDD supply last.

When powering down, remove the PVDD supply first, the VDD supply second, and the VBAT supply last.

Hardware Control Pins

The device has four pins for control and device status: FAULT, MUTE, WARN, and STANDBY.

FAULT

The FAULT pin reports faults and is active low under any of the following conditions:

  • Any channel faults (overcurrent or DC detection)
  • Overtemperature shutdown
  • Overvoltage or undervoltage conditions on the VBAT or PVDD pins
  • Clock errors

The FAULT pin is deactivated when none of the previously listed conditions exist.

Register bits are available to mask fault categories from reporting to the FAULT pin. These bits only mask the setting of the pin and do not affect the register reporting or protection of the device. By default all faults are reported to the pin. See the Register Maps section for a description of the mask settings.

This pin is an open-drain output with an internal 100-kΩ pullup resistor to VDD.

WARN

This active-low output pin reports audio clipping, overtemperature warnings, and POR events.

Clipping is reported if any channel is at the maximum modulation for 20 consecutive PWM clocks which results in a 10-µs delay to report the onset of clipping. The warning bit is sticky and can be cleared by the CLEAR FAULT bit (bit 7) in register 0x21.

An overtemperature warning (OTW) is reported if the general temperature or any of the channel temperature warnings are set. The warning temperature can be set through bits 5 and 6 in register 0x01.

Register bits are available to mask either clipping or OTW reporting to the pin. These bits only mask the setting of the pin and do not affect the register reporting. By default both clipping and OTW are reported.

The WARN pin is latched and can be cleared by writing the CLEAR FAULT bit (bit 7) in register 0x21.

This pin is an open-drain output with an internal 100-kΩ pullup resistor to VDD.

MUTE

This active-low input pin is used for hardware control of the mute and unmute function for all channels.

This pin has a 100-kΩ internal pulldown resistor.

STANDBY

When this active-low input pin is asserted, the device goes into shutdown and current draw is limited. This pin can be used to shut down the device rapidly. The outputs are ramped down in less than 5 ms if the device is not already in the Hi-Z state. The I2C bus goes into the high-impedance (Hi-Z) state when in STANDBY.

This pin has a 100-kΩ internal pulldown resistor.

Device Functional Modes

Operating Modes and Faults

The operating modes and faults are listed in the following tables.

Table 5. Operating Modes

STATE NAMEOUTPUT FETSOSCILLATORI2C
STANDBYHi-ZStoppedStopped
Hi-ZHi-ZActiveActive
MUTESwitching at 50%ActiveActive
PLAYSwitching with audioActiveActive

Table 6. Global Faults and Actions

FAULT/
EVENT
FAULT/EVENT
CATEGORY
MONITORING
MODES
REPORTING
METHOD
ACTION
RESULT
PORVoltage faultAll I2C + WARN pinStandby
VBAT UVHi-Z, mute, normalI2C + FAULT pinHi-Z
PVDD UV
VBAT or PVDD OV
OTWThermal warningHi-Z, mute, normalI2C + WARN pinNone
OTSDThermal shutdownHi-Z, mute, normalI2C + FAULT pinHi-Z

Table 7. Channel Faults and Actions

FAULT/
EVENT
FAULT/EVENT
CATEGORY
MONITORING
MODES
REPORTING
METHOD
ACTION
TYPE
ClippingWarningMute and play WARN pinNone
Overcurrent limitingProtectionCurrent limit
Overcurrent faultOutput channel faultI2C + FAULT pinHi-Z
DC detect

Programming

I2C Serial Communication Bus

The device communicates with the system processor through the I2C serial communication bus as an I2C slave-only device. The processor can poll the device through I2C to determine the operating status, configure settings, or run diagnostics. For a complete list and description of all I2C controls, see the Register Maps section.

The device includes two I2C address pins, so up to four devices can be used together in a system with no additional bus switching hardware. The I2C ADDRx pins set the slave address of the device as listed in Table 8.

Table 8. I2C Addresses

DESCRIPTIONI2C ADDR1I2C ADDR0I2C WriteI2C Read
Device 0 000xD40xD5
Device 1 010xD60xD7
Device 2 100xD80xD9
Device 3 110xDA0xDB

I2C Bus Protocol

The device has a bidirectional serial-control interface that is compatible with the Inter IC (I2C) bus protocol and supports 100-kbps and 400-kbps data transfer rates for random and sequential write and read operations. The TAS6424-Q1 device is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The control interface is used to program the registers of the device and to read device status.

The I2C bus uses two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is HIGH to indicate a start and stop conditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then wait for an acknowledge condition. The device holds SDA LOW during the acknowledge-clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus a R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. The number of bytes that can be transmitted between start and stop conditions is unlimited. When the last word transfers, the master generates a stop condition to release the bus.

TAS6424-Q1 td_i2c_sequence_slos870.gif Figure 41. Typical I2C Sequence
TAS6424-Q1 td_scl-sda_slos870.gif Figure 42. SCL and SDA Timing

Use the I2C ADDRx pins to program the device slave address. Read and write data can be transmitted using single-byte or multiple-byte data transfers.

Random Write

As shown in Figure 43, a single-byte data-write transfer begins with the master device transmitting a start condition followed by the I2C device address and the R/W bit. The R/W bit determines the direction of the data transfer. For a write data transfer, the R/W bit is a 0. After receiving the correct I2C device address and the R/W bit, the device responds with an acknowledge bit. Next, the master transmits the address byte or bytes corresponding to the internal memory address being accessed. After receiving the address byte, the device again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the device again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.

TAS6424-Q1 td_random_write_slos870.gif Figure 43. Random Write Transfer

Sequential Write

A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are transmitted by the master to the device as shown in Figure 44. After receiving each data byte, the device responds with an acknowledge bit and the I2C subaddress is automatically incremented by one.

TAS6424-Q1 td_seq_write_slos870.gif Figure 44. Sequential Write Transfer

Random Read

As shown in Figure 45, a single-byte data-read transfer begins with the master device transmitting a start condition followed by the I2C device address and the R/W bit. For the data-read transfer, both a write followed by a read occur. Initially, a write occurs to transfer the address byte or bytes of the internal memory address to be read. As a result, the R/W bit is a 0. After receiving the address and the R/W bit, the device responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the address and the R/W bit again. This time the R/W bit is a 1, indicating a read transfer. After receiving the address and the R/W bit, the device again responds with an acknowledge bit. Next, the device transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data-read transfer.

TAS6424-Q1 td_random_read_slos870.gif Figure 45. Random Read Transfer

Sequential Read

A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are transmitted by the device to the master device as shown in Figure 46. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte and automatically increments the I2C subaddress by one. After receiving the last data byte, the master device transmits a not-acknowledge bit followed by a stop condition to complete the transfer.

TAS6424-Q1 td_seq_read_slos870.gif Figure 46. Sequential Read Transfer

Register Maps

Table 9. I2C Address Register Definitions

AddressType Register DescriptionSection
0x00R/WMode controlGo
0x01R/WMiscellaneous control 1Go
0x02R/WMiscellaneous control 2Go
0x03R/WSAP control (serial audio-port control)Go
0x04R/WChannel state controlGo
0x05R/WChannel 1 volume controlGo
0x06R/WChannel 2 volume controlGo
0x07R/WChannel 3 volume controlGo
0x08R/WChannel 4 volume controlGo
0x09R/WDC diagnostic control 1Go
0x0AR/WDC diagnostic control 2Go
0x0BR/WDC diagnostic control 3lGo
0x0CRDC load diagnostic report 1 (channels 1 and 2)Go
0x0DRDC load diagnostic report 2 (channels 3 and 4)Go
0x0ERDC load diagnostic report 3—line outputGo
0x0FRChannel state reportingGo
0x10RChannel faults (overcurrent, DC detection) Go
0x11RGlobal faults 1 Go
0x12RGlobal faults 2 Go
0x13RWarnings Go
0x14R/WPin controlGo
0x15R/WAC load diagnostic control 1Go
0x16R/WAC load diagnostic control 2Go
0x17RAC load diagnostic report channel 1Go
0x18RAC load diagnostic report channel 2Go
0x19RAC load diagnostic report channels 3Go
0x1ARAC load diagnostic report channels 4Go
0x1BRAC load diagnostic phase report highGo
0x1CRAC load diagnostic phase report lowGo
0x1DRAC load diagnostic STI report highGo
0x1ERAC load diagnostic STI report lowGo
0x1FRRESERVED
0x20RRESERVED
0x21R/WMiscellaneous control 3Go
0x22R/WClip controlGo
0x23R/WClip windowGo
0x24R/WClip warningGo
0x25R/WILIMIT statusGo
0x26R/WMiscellaneous control 4Go
0x27RRESERVED
0x28R/WRESERVED

Mode Control Register (address = 0x00) [default = 0x00]

The Mode Control register is shown in Figure 47 and described in Table 10.

Figure 47. Mode Control Register
76543210
RESETRESERVEDPBTL CH34PBTL CH12CH1 LO MODECH2 LO MODECH3 LO MODECH4 LO MODE
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0

Table 10. Mode Control Field Descriptions

BitFieldTypeResetDescription
7RESETR/W0

0: Normal operation

1: Resets the device

6RESERVEDR/W0

RESERVED

5PBTL CH34R/W0

0: Channels 3 and 4 are in BTL mode

1: Channels 3 and 4 are in parallel BTL mode

4PBTL CH12R/W0

0: Channels 1 and 2 are in BTL mode

1: Channels 1 and 2 are in parallel BTL mode

3CH1 LO MODER/W0

0: Channel 1 is in normal/speaker mode

1: Channel 1 is in line output mode

2CH2 LO MODER/W0

0: Channel 2 is in normal/speaker mode

1: Channel 2 is in line output mode

1CH3 LO MODER/W0

0: Channel 3 is in normal/speaker mode

1: Channel 3 is in line output mode

0CH4 LO MODER/W0

0: Channel 4 is in normal/speaker mode

1: Channel 4 is in line output mode

Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]

The Miscellaneous Control 1 register is shown in Figure 48 and described in Table 11.

Figure 48. Miscellaneous Control 1 Register
76543210
HPF BYPASSOTW CONTROLOC CONTROLVOLUME RATEGAIN
R/W-0R/W-01R/W-1R/W-00R/W-10

Table 11. Misc Control 1 Field Descriptions

BitFieldTypeResetDescription
7 HPF BYPASSR/W0

0: High pass filter eneabled

1: High pass filter disabled

6–5 OTW CONTROLR/W01

00: Global overtemperature warning set to 140°C

01: Global overtemperature warning set to 130C

10: Global overtemperature warning set to 120°C

11: Global overtemperature warning set to 110°C

4OC CONTROLR/W1

0: Overcurrent is level 1

1: Overcurrent is level 2

3–2VOLUME RATER/W00

00: Volume update rate is 1 step / FSYNC

01: Volume update rate is 1 step / 2 FSYNCs

10: Volume update rate is 1 step / 4 FSYNCs

11: Volume update rate is 1 step / 8 FSYNCs

1–0GAINR/W10

00: Gain level 1 = 7.6-V peak output voltage

01: Gain Level 2 = 15-V peak output voltage

10: Gain Level 3 = 21-V peak output voltage

11: Gain Level 4 = 29-V peak output voltage

Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]

The Miscellaneous Control 2 register is shown in Figure 49 and described in Table 12.

Figure 49. Miscellaneous Control 2 Register
76543210
RESERVEDPWM FREQUENCYRESERVEDSDM_OSROUTPUT PHASE
R/W-110R/W-0R/W-10

Table 12. Misc Control 2 Field Descriptions

BitFieldTypeResetDescription
7RESERVED

0

6–4 PWM FREQUENCY R/W110

000: 8 × fS (352.8 kHz / 384 kHz)

001: 10 × fS (441 kHz / 480 kHz)

010: RESERVED

011: RESERVED

100: RESERVED

101: 38 × fS (1.68 MHz / 1.82 MHz)

110: 44 × fS (1.94 MHz / 2.11 MHz)

111: 48 × fS (2.12 MHz / not supported)

3RESERVED 0 0
2SDM_OSRR/W0

0: 64x OSR

1: 128x OSR

1–0OUTPUT PHASER/W10

00: 0 degrees output-phase switching offset

01: 30 degrees output-phase switching offset

10: 45 degrees output-phase switching offset

11: 60 degrees output-phase switching offset

SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]

The SAP Control (serial audio-port control) register is shown in Figure 50 and described in Table 13.

Figure 50. SAP Control Register
76543210
INPUT SAMPLING RATE8 Ch TDM SLOT SELECTTDM SLOT SIZETDM SLOT SELECT 2INPUT FORMAT
R/W-00R/W-0R/W-0R/W-0R/W-100

Table 13. SAP Control Field Descriptions

BitFieldTypeResetDescription
7–6 INPUT SAMPLING RATE R/W00

00: 44.1 kHz

01: 48 kHz

10: 96 kHz

11: RESERVED

5 8 Ch TDM SLOT SELECT R/W0

0: First four TDM slots

1: Last four TDM slots

4TDM SLOT SIZER/W0

0: TDM slot size is 24-bit or 32-bit

1: TDM slot size is 16-bit

3TDM SLOT SELECT 2R/W0

0: Normal

1: swap channel 1/2 with channel 3/4

2–0INPUT FORMATR/W100

000: 24-bit right justified

001: 20-bit right justified

010: 18-bit right justified

011: 16-bit right justified

100: I2S (16-bit or 24-bit)

101: Left justified (16-bit or 24-bit)

110: TDM mode (16-bit or 24-bit)

111: RESERVED

Channel State Control Register (address = 0x04) [default = 0x55]

The Channel State Control register is shown in Figure 51 and described in Table 14.

Figure 51. Channel State Control Register
76543210
CH1 STATE CONTROLCH2 STATE CONTROLCH3 STATE CONTROLCH4 STATE CONTROL
R/W-01R/W-01R/W-01R/W-01

Table 14. Channel State Control Field Descriptions

BitFieldTypeResetDescription
7–6 CH1 STATE CONTROL R/W01

00: PLAY

01: Hi-Z

10: MUTE

11: DC load diagnostics

5–4 CH2 STATE CONTROL R/W01

00: PLAY

01: Hi-Z

10: MUTE

11: DC load diagnostics

3–2CH3 STATE CONTROLR/W01

00: PLAY

01: Hi-Z

10: MUTE

11: DC load diagnostics

1–0CH4 STATE CONTROLR/W01

00: PLAY

01: Hi-Z

10: MUTE

11: DC load diagnostics

Channel 1 Through 4 Volume Control Registers (address = 0x05–0x088) [default = 0xCF]

The Channel 1 Through 4 Volume Control registers are shown in Figure 52 and described in Table 15.

Figure 52. Channel x Volume Control Register
76543210
CH x VOLUME
R/W-CF

Table 15. Ch x Volume Control Field Descriptions

BitFieldTypeResetDescription
7–0 CH x VOLUME R/WCF

8-Bit Volume Control for each channel, register address for Ch1 is 0x05, Ch2 is 0x06, Ch3 is 0x07 and Ch4 is 0x08, 0.5 dB/step:

0xFF: 24 dB

0xCF: 0 dB

0x07: –100 dB

< 0x07: MUTE

DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]

The DC Diagnostic Control 1 register is shown in Figure 53 and described in Table 16.

Figure 53. DC Load Diagnostic Control 1 Register
76543210
DC LDG ABORT2x_RAMP2x_SETTLERESERVEDLDG LO ENABLELDG BYPASS
R/W-0R/W-0R/W-0R/W-0R/W-0

Table 16. DC Load Diagnostics Control 1 Field Descriptions

BitFieldTypeResetDescription
7 DC LDG ABORT R/W0

0: Default state, clear after abort

1: Aborts the load diagnostics in progress

62x_RAMPR/W0

0: Normal ramp time

1: Double ramp time

52x_SETTLER/W0

0: Normal Settle time

1: Double setling time

4–2 RESERVED 0

0

1LDG LO ENABLER/W0

0: Line output diagnostics are disabled

1: Line output diagnostics are enabled

0LDG BYPASSR/W0

0: Automatic diagnostics when leaving Hi-Z and after channel fault

1: Diagnostics are not run automatically

DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]

The DC Diagnostic Control 2 register is shown in Figure 54 and described in Table 17.

Figure 54. DC Load Diagnostic Control 2 Register
76543210
CH1 DC LDG SLCH2 DC LDG SL
R/W-0001R/W-0001

Table 17. DC Load Diagnostics Control 2 Field Descriptions

BitFieldTypeResetDescription
7–4 CH1 DC LDG SL R/W0001

DC load diagnostics shorted-load threshold

0000: 0.5 Ω

0001: 1 Ω

0010: 1.5 Ω

...

1001: 5 Ω

3–0 CH2 DC LDG SL R/W0001

DC load diagnostics shorted-load threshold

0000: 0.5 Ω

0001: 1 Ω

0010: 1.5 Ω

...

1001: 5 Ω

DC Load Diagnostic Control 3 Register (address = 0x0B) [default = 0x11]

The DC Diagnostic Control 3 register is shown in Figure 55 and described in Table 18.

Figure 55. DC Load Diagnostic Control 3 Register
76543210
CH3 DC LDG SLCH4 DC LDG SL
R/W-0001R/W-0001

Table 18. DC Load Diagnostics Control 3 Field Descriptions

BitFieldTypeResetDescription
7–4 CH3 DC LDG SLR/W0001

DC load diagnostics shorted-load threshold

0000: 0.5 Ω

0001: 1 Ω

0010: 1.5 Ω

...

1001: 5 Ω

3–0 CH4 DC LDG SLR/W0001

DC load diagnostics shorted-load threshold

0000: 0.5 Ω

0001: 1 Ω

0010: 1.5 Ω

...

1001: 5 Ω

DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]

DC Load Diagnostic Report 1 register is shown in Figure 56 and described in Table 19.

Figure 56. DC Load Diagnostic Report 1 Register
76543210
CH1 S2GCH1 S2PCH1 OLCH1 SLCH2 S2GCH2 S2PCH2 OLCH2 SL
R-0R-0R-0R-0R-0R-0R-0R-0

Table 19. DC Load Diagnostics Report 1 Field Descriptions

BitFieldTypeResetDescription
7CH1 S2GR0

0: No short-to-GND detected

1: Short-To-GND Detected

6CH1 S2PR0

0: No short-to-power detected

1: Short-to-power detected

5CH1 OLR0

0: No open load detected

1: Open load detected

4CH1 SLR0

0: No shorted load detected

1: Shorted load detected

3CH2 S2GR0

0: No short-to-GND detected

1: Short-to-GND detected

2CH2 S2PR0

0: No short-to-power detected

1: Short-to-power detected

1CH2 OLR0

0: No open load detected

1: Open load detected

0CH2 SLR0

0: No shorted load detected

1: Shorted load detected

DC Load Diagnostic Report 2 Register (address = 0x0D) [default = 0x00]

The DC Load Diagnostic Report 2 register is shown in Figure 57 and described in Table 20.

Figure 57. DC Load Diagnostic Report 2 Register
76543210
CH3 S2GCH3 S2PCH3 OLCH3 SLCH4 S2GCH4 S2PCH4 OLCH4 SL
R-0R-0R-0R-0R-0R-0R-0R-0

Table 20. DC Load Diagnostics Report 2 Field Descriptions

BitFieldTypeResetDescription
7CH3 S2GR0

0: No short-to-GND detected

1: Short-to-GND detected

6CH3 S2PR0

0: No short-to-power detected

1: Short-to-power detected

5CH3 OLR0

0: No open load detected

1: Open load detected

4CH3 SLR0

0: No shorted load detected

1: Shorted load detected

3CH4 S2GR0

0: No short-to-GND detected

1: Short-to-GND detected

2CH4 S2PR0

0: No short-to-power detected

1: Short-to-power detected

1CH4 OLR0

0: No open load detected

1: Open load detected

0CH4 SLR0

0: No shorted load detected

1: Shorted load detected

DC Load Diagnostics Report 3—Line Output—Register (address = 0x0E) [default = 0x00]

The DC Load Diagnostic Report, Line Output, register is shown in Figure 58 and described in Table 21.

Figure 58. DC Load Diagnostics Report 3—Line Output—Register
76543210
RESERVEDCH1 LO LDGCH2 LO LDGCH3 LO LDGCH4 LO LDG
R-0R-0R-0R-0

Table 21. DC Load Diagnostics Report 3—Line Output—Field Descriptions

BitFieldTypeResetDescription
7–4 RESERVED

0

3CH1 LO LDGR0

0: No line output detected on channel 1

1: Line output detected on channel 1

2CH2 LO LDGR0

0: No line output detected on channel 2

1: Line output detected on channel 2

1CH3 LO LDGR0

0: No line output detected on channel 3

1: Line output detected on channel 3

0CH4 LO LDGR0

0: No line output detected on channel 4

1: Line output detected on channel 3

Channel State Reporting Register (address = 0x0F) [default = 0x55]

The Channel State Reporting register is shown in Figure 59 and described in Table 22.

Figure 59. Channel State-Reporting Register
76543210
CH1 STATE REPORTCH2 STATE REPORTCH3 STATE REPORTCH3 STATE REPORT
R-01R-01R-01R-01

Table 22. State-Reporting Field Descriptions

BitFieldTypeResetDescription
7–6 CH1 STATE REPORTR01

00: PLAY

01: Hi-Z

10: MUTE

11: DC load diagnostics

5–4 CH2 STATE REPORTR01

00: PLAY

01: Hi-Z

10: MUTE

11: DC load diagnostics

3–2CH3 STATE REPORTR01

00: PLAY

01: Hi-Z

10: MUTE

11: DC load diagnostics

1–0CH4 STATE REPORTR01

00: PLAY

01: Hi-Z

10: MUTE

11: DC load diagnostics

Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]

The Channel Faults (overcurrent, DC detection) register is shown in Figure 60 and described in Table 23.

Figure 60. Channel Faults Register
76543210
CH1 OCCH2 OCCH3 OCCH4 OCCH1 DCCH2 DCCH3 DCCH4 DC
R-0R-0R-0R-0R-0R-0R-0R-0

Table 23. Channel Faults Field Descriptions

BitFieldTypeResetDescription
7CH1 OCR0

0: No overcurrent fault detected

1: Overcurrent fault detected

6CH2 OCR0

0: No overcurrent fault detected

1: Overcurrent fault detected

5CH3 OCR0

0: No overcurrent fault detected

1: Overcurrent fault detected

4CH4 OCR0

0: No overcurrent fault detected

1: Overcurrent fault detected

3CH1 DCR0

0: No DC fault detected

1: DC fault detected

2CH2 DCR0

0: No DC fault detected

1: DC fault detected

1CH3 DCR0

0: No DC fault detected

1: Overcurrent fault detected

0CH4 DCR0

0: No DC fault detected

1: Overcurrent fault detected

Global Faults 1 Register (address = 0x11) [default = 0x00]

The Global Faults 1 register is shown in Figure 61 and described in Table 24.

Figure 61. Global Faults 1 Register
76543210
RESERVEDINVALID CLOCKPVDD OVVBAT OVPVDD UVVBAT UV
R-0R-0R-0R-0R-0

Table 24. Global Faults 1 Field Descriptions

BitFieldTypeResetDescription
7–5RESERVED0

0

4INVALID CLOCKR0

0: No clock fault detected

1: Clock fault detected

3PVDD OVR0

0: No PVDD overvoltage fault detected

1: PVDD overvoltage fault detected

2VBAT OVR0

0: No VBAT overvoltage fault detected

1: VBAT overvoltage fault detected

1PVDD UVR0

0: No PVDD undervoltage fault detected

1: PVDD undervoltage fault detected

0VBAT UVR0

0: No VBAT undervoltage fault detected

1: VBAT undervoltage fault detected

Global Faults 2 Register (address = 0x12) [default = 0x00]

The Global Faults 2 register is shown in Figure 62 and described in Table 25.

Figure 62. Global Faults 2 Register
76543210
RESERVEDOTSDCH1 OTSDCH2 OTSDCH3 OTSDCH4 OTSD
R-0R-0R-0R-0R-0

Table 25. Global Faults 2 Field Descriptions

BitFieldTypeResetDescription
7–5 RESERVED

0

4OTSDR0

0: No global overtemperature shutdown

1: Global overtemperature shutdown

3CH1 OTSDR0

0: No overtemperature shutdown on Ch1

1: Overtemperature shutdown on Ch1

2CH2 OTSDR0

0: No overtemperature shutdown on Ch2

1: Overtemperature shutdown on Ch2

1CH3 OTSDR0

0: No overtemperature shutdown on Ch4

1: Overtemperature shutdown on Ch4

0CH4 OTSDR0

0: No overtemperature shutdown on Ch4

1: Overtemperature shutdown on Ch4

Warnings Register (address = 0x13) [default = 0x20]

The Warnings register is shown in Figure 63 and described in Table 26.

Figure 63. Warnings Register
76543210
RESERVEDVDD POROTWOTW CH1OTW CH2OTW CH3OTW CH4
R-0R-0R-0R-0R-0R-0

Table 26. Warnings Field Descriptions

BitFieldTypeResetDescription
7 -6RESERVED00

0

5VDD PORR0

0: No VDD POR has occurred

1 VDD POR occurred

4OTWR0

0: No global overtemperature warning

1: Global overtemperature warning

3OTW CH1R0

0: No overtemperature warning on channel 1

1: Overtemperature warning on channel 1

2OTW CH2R0

0: No overtemperature warning on channel 2

1: Overtemperature warning on channel 2

1OTW CH4R0

0: No overtemperature warning on channel 4

1: Overtemperature warning on channel 4

0OTW CH4R0

0: No overtemperature warning on channel 4

1: Overtemperature warning on channel 4

Pin Control Register (address = 0x14) [default = 0xFF]

The Pin Control register is shown in Figure 64 and described in Table 27.

Figure 64. Pin Control Register
76543210
MASK OCMASK OTSDMASK UVMASK OVMASK DCMASK ILIMITMASK CLIPMASK OTW
R/W-1R/W-1R/W-1R/W-1R/W-1R/W-1R/W-1R/W-1

Table 27. Pin Control Field Descriptions

BitFieldTypeResetDescription
7MASK OCR/W1

0: Do not report overcurrent faults on the FAULT pin

1: Report overcurrent faults on the FAULT Pin

6MASK OTSDR/W1

0: Do not report overtemperature faults on the FAULT pin

1: Report overtemperature faults on the FAULT pin

5MASK UVR/W1

0: Do not report overvoltage faults on the FAULT pin

1: Report overvoltage faults on the FAULT pin

4MASK OVR/W1

0: Do not report undervoltage faults on the FAULT pin

1: Report undervoltage faults on the FAULT pin

3MASK DCR/W1

0: Do not report DC faults on the FAULT pin

1: Report DC faults on the FAULT pin

2MASK ILIMITR/W1

0: Do not report Ilimit on the FAULT pin

1: Report Ilimit on the FAULT pin

1MASK CLIPR/W1

0: Do not report clipping on the WARN pin

1: Report clipping on the WARN pin

0MASK OTWR/W1

0: Do not report overtemperature warnings on the WARN pin

1: Report overtemperature warnings on the WARN pin

AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]

The AC Load Diagnostic Control 1 register is shown in Figure 65 and described in Table 28.

Figure 65. AC Load Diagnostic Control 1 Register
76543210
CH1 GAINRESERVEDCH3 GAINRESERVEDCH1 ENABLECH2 ENABLECH3 ENABLECH4 ENABLE
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0

Table 28. AC Load Diagnostic Control 1 Field Descriptions

BitFieldTypeResetDescription
7CH1, CH2, PBTL12: GAINR/W0

0: Gain 1

1: Gain 4

6RESERVEDR/W0 0
5CH3, CH4, PBTL34: GAINR/W0

0: Gain 1

1: Gain 4

4RESERVEDR/W0 0
3CH1 ENABLER/W0

0: AC diagnostics disabled

1: Enable AC diagnostics

2CH2 ENABLER/W0

0: AC diagnostics disabled

1: Enable AC diagnostics

1CH3 ENABLER/W0

0: AC diagnostics disabled

1: Enable AC diagnostics

0CH4 ENABLER/W0

0: AC diagnostics disabled

1: Enable AC diagnostics

AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]

The AC Load Diagnostic Control 1 register is shown in Figure 65 and described in Table 28.

Figure 66. AC Load Diagnostic Control 2 Register
76543210
AC_DIAGS_LOOPBACKRESERVEDAC TIMINGAC CURRENTRESERVED
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0

Table 29. AC Load Diagnostic Control 2 Field Descriptions

BitFieldTypeResetDescription
7AC_DIAGS_LOOPBACKR/W0

0: disable AC Diag loopback

1: Enable AC Diag loopback

6-5RESERVEDR/W0000
4AC TIMINGR/W0

0: 32 Cycles

1: 64 Cycles

3-2AC CURRENTR/W00

00: 10mA

01: 19 mA

10: RESERVED

11: RESERVED

1-0RESERVEDR/W00 00

AC Load Diagnostic Impedance Report Ch1 through CH4 Registers (address = 0x17–0x1A) [default = 0x00]

The AC Load Diagnostic Report Ch1 through CH4 registers are shown in Figure 67 and described in Table 30.

Figure 67. AC Load Diagnostic Impedance Report Chx Register
76543210
CHx IMPEDANCE
R-00

Table 30. Chx AC LDG Impedance Report Field Descriptions

BitFieldTypeResetDescription
7–0 CH x IMPEDANCE R00

8-bit AC-load diagnostic report for each channel with a step size of 0.2496 Ω/bit (control by register 0x15 and register 0x16)

0x00: 0 Ω

0x01: 0.2496 Ω

...

0xFF: 63.65 Ω

AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]

The AC Load Diagnostic Phase High value registers are shown in Figure 68 and described in Table 31.

Figure 68. AC Load Diagnostic (LDG) Phase High Report Register
76543210
AC Phase High
R-00

Table 31. AC LDG Phase High Report Field Descriptions

BitFieldTypeResetDescription
7–0 AC Phase HighR00Bit 15:8

AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]

The AC Load Diagnostic Phase Low value registers are shown in Figure 69 and described in Table 32.

Figure 69. AC Load Diagnostic (LDG) Phase Low Report Register
76543210
AC Phase Low
R-00

Table 32. AC LDG Phase Low Report Field Descriptions

BitFieldTypeResetDescription
7–0 AC Phase LowR00Bit 7:0

AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]

The AC Load Diagnostic STI High value registers are shown in Figure 70 and described in Table 33.

Figure 70. AC Load Diagnostic (LDG) STI High Report Register
76543210
AC STI High
R-00

Table 33. AC LDG STI High Report Field Descriptions

BitFieldTypeResetDescription
7–0 AC STI HighR00Bit 15:8

AC Load Diagnostic STI Report Low Register (address = 0x1C) [default = 0x00]

The AC Load Diagnostic STI Low value registers are shown in Figure 67 and described in Table 34.

Figure 71. AC Load Diagnostic (LDG) STI Low Report Register
76543210
AC STI Low
R-00

Table 34. Chx AC LDG STI Low Report Field Descriptions

BitFieldTypeResetDescription
7–0 AC STI LowR00Bit 7:0

Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]

The Miscellaneous Control 3 register is shown in Figure 73 and described in Table 35.

Figure 72. Miscellaneous Control 3 Register
76543210
CLEAR FAULTPBTL_CH_SELMASK ILIMIT WARNINGRESERVEDOTSD AUTO RECOVERYRESERVED
R/W-0R/W-0R/W-0R/W-1R/W-0

Table 35. Misc Control 3 Field Descriptions

BitFieldTypeResetDescription
7CLEAR FAULTR/W0

0: Normal operation

1: Clear fault

6 PBTL_CH_SELR/W0

0: PBTL normal signal source

1: PBTL flip signal source

5MASK ILIMIT WARNINGR/W0

0: Report ILIMIT on the WARN pin

1: Do not report ILIMIT on the WARN pin

4RESERVEDR/W0

0

3 OTSD AUTO RECOVERY R/W0

0: Report overtemperature faults on the FAULT pin

0: Automatic temperature protection recovery. Do not report overtemperature faults on the FAULT pin

2–0RESERVED 0

0

Clip Control Register (address = 0x22) [default = 0x01]

The Clip Detect register is shown in Figure 73 and described in Table 36.

Figure 73. Clip Control Register
76543210
RESERVEDCLIPDET_EN
R/W-1

Table 36. Clip Control Field Descriptions

BitFieldTypeResetDescription
7-1 RESERVED

0

0CLIPDET_EN R/W1

0: Clip detect disable

1: Clip Detect Enable

Clip Window Register (address = 0x23) [default = 0x14]

The Clip Window register is shown in Figure 74 and described in Table 37.

Figure 74. Clip Window Register
76543210
CLIP_WINDOW_SEL[7:1]
R/W-00001110

Table 37. Clip Window Field Descriptions

BitFieldTypeResetDescription
7-0 CLIP_WINDOW_SEL[7:1] R/W00010100

00000000

00000001

00000010

00000011

00000100

00000101

00000110

00000111

00001000

00001001

00001010

00001110

00010100

Clip Warning Register (address = 0x24) [default = 0x00]

The Clip Window register is shown in Figure 75 and described in Table 38.

Figure 75. Clip Warning Register
76543210
RESERVEDCH4_CLIPCH4_CLIPCH2_CLIPCH1_CLIP
R-0R-0R-0R-0

Table 38. Clip Warning Field Descriptions

BitFieldTypeResetDescription
7-4 RESERVED 0

0

3CH4_CLIPR0

0: No Clip Detect

1: Clip Detect

2CH3_CLIPR0

0: No Clip Detect

1: Clip Detect

1CH2_CLIPR0

0: No Clip Detect

1: Clip Detect

0CH1_CLIPR0

0: No Clip Detect

1: Clip Detect

ILIMIT Status Register (address = 0x25) [default = 0x00]

The ILIMIT Status register is shown in Figure 76 and described in Table 39.

Figure 76. ILIMIT Status Register
76543210
RESERVEDCH4_ILIMIT_WARNCH3_ILIMIT_WARNCH2_ILIMIT_WARNCH1_ILIMIT_WARN
R-0R-0R-0R-0

Table 39. ILIMIT Status Field Descriptions

BitFieldTypeResetDescription
7 RESERVED00
6RESERVED00
5RESERVED00
4RESERVED00
3CH4_ILIMIT_WARNR0

0: No ILIMIT

1: ILIMIT Warning

2CH3_ILIMIT_WARNR0

0: No ILIMIT

1: ILIMIT Warning

1CH2_ILIMIT_WARNR0

0: No ILIMIT

1: ILIMIT Warning

0CH1_ILIMIT_WARNR0

0: No ILIMIT

1: ILIMIT Warning

Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]

The Miscellaneous Control 4 register is shown in Figure 77 and described in Table 40.

Figure 77. Miscellaneous Control 4 Register
76543210
RESERVEDHPF_CORNER[2:0]
R/W-00000R/W-000

Table 40. Misc Control 4 Field Descriptions

BitFieldTypeResetDescription
7-3RESERVEDR/W01000

01000: DEFAULT

2-0 HPF_CORNER[2:0]R/W000

000: 3.7 Hz

001: 7.4 Hz

010: 15 Hz

011: 30 Hz

100: 59 Hz

101: 118 Hz

110: 235 Hz

111: 463 Hz