SLOS870B September 2016  – October 2017 TAS6424-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5Electrical Characteristics
    6. 7.6Timing Requirements
    7. 7.7Typical Characteristics
  8. Parameter measurement Information
  9. Detailed description
    1. 9.1Overview
    2. 9.2Functional Block Diagram
    3. 9.3Feature Description
      1. 9.3.1 Serial Audio Port
        1. I2S Mode
        2. Timing
        3. Timing
        4. Mode
        5. Clock Rates
        6. Error Handling
      2. 9.3.2 High-Pass Filter
      3. 9.3.3 Volume Control and Gain
      4. 9.3.4 High-Frequency Pulse-Width Modulator (PWM)
      5. 9.3.5 Gate Drive
      6. 9.3.6 Power FETs
      7. 9.3.7 Load Diagnostics
        1. Load Diagnostics
        2. Output Diagnostics
        3. Load Diagnostics
      8. 9.3.8 Protection and Monitoring
        1. Limit (ILIMIT)
        2. Shutdown (ISD)
        3. Detect
        4. Detect
        5. Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)
        6. Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]
        7. (UV) and Power-On-Reset (POR)
        8. (OV) and Load Dump
      9. 9.3.9 Power Supply
        1. Power-Supply Sequence
        2. Power-Supply Sequence
      10. 9.3.10Hardware Control Pins
    4. 9.4Device Functional Modes
      1. 9.4.1Operating Modes and Faults
    5. 9.5Programming
      1. 9.5.1I2C Serial Communication Bus
      2. 9.5.2I2C Bus Protocol
      3. 9.5.3Random Write
      4. 9.5.4Sequential Write
      5. 9.5.5Random Read
      6. 9.5.6Sequential Read
    6. 9.6Register Maps
      1. 9.6.1 Mode Control Register (address = 0x00) [default = 0x00]
      2. 9.6.2 Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
      3. 9.6.3 Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
      4. 9.6.4 SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]
      5. 9.6.5 Channel State Control Register (address = 0x04) [default = 0x55]
      6. 9.6.6 Channel 1 Through 4 Volume Control Registers (address = 0x05-0x088) [default = 0xCF]
      7. 9.6.7 DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
      8. 9.6.8 DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
      9. 9.6.9 DC Load Diagnostic Control 3 Register (address = 0x0B) [default = 0x11]
      10. 9.6.10DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
      11. 9.6.11DC Load Diagnostic Report 2 Register (address = 0x0D) [default = 0x00]
      12. 9.6.12DC Load Diagnostics Report 3—Line Output—Register (address = 0x0E) [default = 0x00]
      13. 9.6.13Channel State Reporting Register (address = 0x0F) [default = 0x55]
      14. 9.6.14Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]
      15. 9.6.15Global Faults 1 Register (address = 0x11) [default = 0x00]
      16. 9.6.16Global Faults 2 Register (address = 0x12) [default = 0x00]
      17. 9.6.17Warnings Register (address = 0x13) [default = 0x20]
      18. 9.6.18Pin Control Register (address = 0x14) [default = 0xFF]
      19. 9.6.19AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
      20. 9.6.20AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
      21. 9.6.21AC Load Diagnostic Impedance Report Ch1 through CH4 Registers (address = 0x17-0x1A) [default = 0x00]
      22. 9.6.22AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]
      23. 9.6.23AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]
      24. 9.6.24AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]
      25. 9.6.25AC Load Diagnostic STI Report Low Register (address = 0x1C) [default = 0x00]
      26. 9.6.26Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
      27. 9.6.27Clip Control Register (address = 0x22) [default = 0x01]
      28. 9.6.28Clip Window Register (address = 0x23) [default = 0x14]
      29. 9.6.29Clip Warning Register (address = 0x24) [default = 0x00]
      30. 9.6.30ILIMIT Status Register (address = 0x25) [default = 0x00]
      31. 9.6.31Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]
  10. 10Application and Implementation
    1. 10.1Application Information
      1. 10.1.1AM-Radio Band Avoidance
      2. 10.1.2Parallel BTL Operation (PBTL)
      3. 10.1.3Demodulation Filter Design
      4. 10.1.4Line Driver Applications
    2. 10.2Typical Applications
      1. 10.2.1BTL Application
        1. Requirements
        2. Supplies
        4. Design Procedure
          1. Design
          2. Input and the Serial Audio Port
          3. Capacitors
          4. Reconstruction Filter
        5. Curves
      2. 10.2.2PBTL Application
        1. Requirements
          1. Design Procedure
        2. Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1Layout Guidelines
      1. 12.1.1Electrical Connection of Thermal pad and Heat Sink
      2. 12.1.2EMI Considerations
      3. 12.1.3General Guidelines
    2. 12.2Layout Example
    3. 12.3Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1Documentation Support
      1. 13.1.1Related Documentation
    2. 13.2Receiving Notification of Documentation Updates
    3. 13.3Community Resources
    4. 13.4Trademarks
    5. 13.5Electrostatic Discharge Caution
    6. 13.6Glossary
  14. 14Mechanical, Packaging, and Orderable Information


Layout Guidelines

The pinout of the TAS6424-Q1 was selected to provide flowthrough layout with all high-power connections on the right side, and all low-power signals and supply decoupling on the left side.

Figure 85 shows the area for the components in the application example (see the Typical Applications section).

The TAS6424-Q1 EVM uses a four-layer PCB. The copper thickness was selected as 70 µm to optimize power loss.

The small value of the output filter provides a small size and, in this case, the low height of the inductor enables double-sided mounting.

The EVM PCB shown in Figure 85 is the basis for the layout guidelines.

Electrical Connection of Thermal pad and Heat Sink

For the DKQ package, the heat sink connected to the thermal pad of the device should be connected to GND. The heat slug must not be connected to any other electrical node.

EMI Considerations

Automotive-level EMI performance depends on both careful integrated circuit design and good system-level design. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of the design. The design has minimal parasitic inductances because of the short leads on the package which reduces the EMI that results from current passing from the die to the system PCB. Each channel also operates at a different phase. The design also incorporates circuitry that optimizes output transitions that cause EMI.

For optimizing the EMI a solid ground layer plane is recommended, for a PCB design the fulfills the CISPR25 level 5 requirements, see the TAS6424-Q1 EVM layout.

General Guidelines

The EVM layout is optimized for low noise and EMC performance.

The TAS6424-Q1 has an exposed thermal pad that is up, away from the PCB. The layout must consider an external heat sink.

Refer to Figure 85 for the following guidelines:

  • A ground plane, A, on the same side as the device pins helps reduce EMI by providing a very-low loop impedance for the high-frequency switching current.
  • The decoupling capacitors on PVDD, B, are very close to the device with the ground return close to the ground pins.
  • The ground connections for the capacitors in the LC filter, C, have a direct path back to the device and also the ground return for each channel is the shared. This direct path allows for improved common mode EMI rejection.
  • The traces from the output pins to the inductors, D, should have the shortest trace possible to allow for the smallest loop of large switching currents.
  • Heat-sink mounting screws, E, should be close to the device to keep the loop short from the package to ground.
  • Many vias, F, stitching together the ground planes can create a shield to isolate the amplifier and power supply.

Layout Example

TAS6424-Q1 EVM_LAYOUT_SLOS870.gif Figure 85. EVM Layout

Thermal Considerations

The thermally enhanced PowerPAD package has an exposed pad up for connection to a heat sink. The output power of any amplifier is determined by the thermal performance of the amplifier as well as limitations placed on it by the system, such as the ambient operating temperature. The heat sink absorbs heat from the TAS6424-Q1 and transfers it to the air. With proper thermal management this process can reach equilibrium and heat can be continually transferred from the device. Heat sinks can be smaller than that of classic linear amplifier design because of the excellent efficiency of class-D amplifiers. This device is intended for use with a heat sink, therefore, RθJC will be used as the thermal resistance from junction to the exposed metal package. This resistance will dominate the thermal management, so other thermal transfers will not be considered. The thermal resistance of RθJA (junction to ambient) is required to determine the full thermal solution. The thermal resistance is comprised of the following components:

  • RθJC of the TAS6424-Q1
  • Thermal resistance of the thermal interface material
  • Thermal resistance of the heat sink

The thermal resistance of the thermal interface material can be determined from the manufacturer’s value for the area thermal resistance (expressed in °C-mm2/W) and the area of the exposed metal package. For example, a typical, white, thermal grease with a 0.0254-mm (0.001-inch) thick layer is approximately 4.52°C-mm2/W. The TAS6424-Q1 in the DKQ package has an exposed area of 47.6 mm2. By dividing the area thermal resistance by the exposed metal area determines the thermal resistance for the thermal grease. The thermal resistance of the thermal grease is 0.094°C/W

Table 41 lists the modeling parameters for one device on a heat sink. The junction temperature is assumed to be 115°C while delivering and average power of 10 watts per channel into a 4-Ω load. The thermal-grease example previously described is used for the thermal interface material. Use Equation 1 to design the thermal system.

Equation 1. RθJA = RθJC + thermal interface resistance + heat sink resistance

Table 41. Thermal Modeling

Ambient Temperature25°C
Average Power to load40W (4x 10w)
Power dissipation8W (4x 2w)
Junction Temperature115°C
ΔT inside package5.6°C (0.7°C/W × 8W)
ΔT through thermal interface material0.75°C (0.094°C/W × 8W)
Required heat sink thermal resistance10.45°C/W ([115°C – 25°C – 5.6°C – 0.75°C] / 8W)
System thermal resistance to ambient RθJA11.24°C/W