SLOS870B September 2016  – October 2017 TAS6424-Q1

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5Electrical Characteristics
    6. 7.6Timing Requirements
    7. 7.7Typical Characteristics
  8. Parameter measurement Information
  9. Detailed description
    1. 9.1Overview
    2. 9.2Functional Block Diagram
    3. 9.3Feature Description
      1. 9.3.1 Serial Audio Port
        1. 9.3.1.1 I2S Mode
        2. 9.3.1.2Left-Justified Timing
        3. 9.3.1.3Right-Justified Timing
        4. 9.3.1.4TDM Mode
        5. 9.3.1.5Supported Clock Rates
        6. 9.3.1.6Audio-Clock Error Handling
      2. 9.3.2 High-Pass Filter
      3. 9.3.3 Volume Control and Gain
      4. 9.3.4 High-Frequency Pulse-Width Modulator (PWM)
      5. 9.3.5 Gate Drive
      6. 9.3.6 Power FETs
      7. 9.3.7 Load Diagnostics
        1. 9.3.7.1DC Load Diagnostics
        2. 9.3.7.2Line Output Diagnostics
        3. 9.3.7.3AC Load Diagnostics
      8. 9.3.8 Protection and Monitoring
        1. 9.3.8.1Overcurrent Limit (ILIMIT)
        2. 9.3.8.2Overcurrent Shutdown (ISD)
        3. 9.3.8.3DC Detect
        4. 9.3.8.4Clip Detect
        5. 9.3.8.5Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)
        6. 9.3.8.6Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]
        7. 9.3.8.7Undervoltage (UV) and Power-On-Reset (POR)
        8. 9.3.8.8Overvoltage (OV) and Load Dump
      9. 9.3.9 Power Supply
        1. 9.3.9.1Vehicle-Battery Power-Supply Sequence
        2. 9.3.9.2Boosted Power-Supply Sequence
      10. 9.3.10Hardware Control Pins
        1. 9.3.10.1FAULT
        2. 9.3.10.2WARN
        3. 9.3.10.3MUTE
        4. 9.3.10.4STANDBY
    4. 9.4Device Functional Modes
      1. 9.4.1Operating Modes and Faults
    5. 9.5Programming
      1. 9.5.1I2C Serial Communication Bus
      2. 9.5.2I2C Bus Protocol
      3. 9.5.3Random Write
      4. 9.5.4Sequential Write
      5. 9.5.5Random Read
      6. 9.5.6Sequential Read
    6. 9.6Register Maps
      1. 9.6.1 Mode Control Register (address = 0x00) [default = 0x00]
      2. 9.6.2 Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
      3. 9.6.3 Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
      4. 9.6.4 SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]
      5. 9.6.5 Channel State Control Register (address = 0x04) [default = 0x55]
      6. 9.6.6 Channel 1 Through 4 Volume Control Registers (address = 0x05-0x088) [default = 0xCF]
      7. 9.6.7 DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
      8. 9.6.8 DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
      9. 9.6.9 DC Load Diagnostic Control 3 Register (address = 0x0B) [default = 0x11]
      10. 9.6.10DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
      11. 9.6.11DC Load Diagnostic Report 2 Register (address = 0x0D) [default = 0x00]
      12. 9.6.12DC Load Diagnostics Report 3—Line Output—Register (address = 0x0E) [default = 0x00]
      13. 9.6.13Channel State Reporting Register (address = 0x0F) [default = 0x55]
      14. 9.6.14Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]
      15. 9.6.15Global Faults 1 Register (address = 0x11) [default = 0x00]
      16. 9.6.16Global Faults 2 Register (address = 0x12) [default = 0x00]
      17. 9.6.17Warnings Register (address = 0x13) [default = 0x20]
      18. 9.6.18Pin Control Register (address = 0x14) [default = 0xFF]
      19. 9.6.19AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
      20. 9.6.20AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
      21. 9.6.21AC Load Diagnostic Impedance Report Ch1 through CH4 Registers (address = 0x17-0x1A) [default = 0x00]
      22. 9.6.22AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]
      23. 9.6.23AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]
      24. 9.6.24AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]
      25. 9.6.25AC Load Diagnostic STI Report Low Register (address = 0x1C) [default = 0x00]
      26. 9.6.26Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
      27. 9.6.27Clip Control Register (address = 0x22) [default = 0x01]
      28. 9.6.28Clip Window Register (address = 0x23) [default = 0x14]
      29. 9.6.29Clip Warning Register (address = 0x24) [default = 0x00]
      30. 9.6.30ILIMIT Status Register (address = 0x25) [default = 0x00]
      31. 9.6.31Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]
  10. 10Application and Implementation
    1. 10.1Application Information
      1. 10.1.1AM-Radio Band Avoidance
      2. 10.1.2Parallel BTL Operation (PBTL)
      3. 10.1.3Demodulation Filter Design
      4. 10.1.4Line Driver Applications
    2. 10.2Typical Applications
      1. 10.2.1BTL Application
        1. 10.2.1.1Design Requirements
        2. 10.2.1.2Power Supplies
        3. 10.2.1.3Communication
        4. 10.2.1.4Detailed Design Procedure
          1. 10.2.1.4.1Hardware Design
          2. 10.2.1.4.2Digital Input and the Serial Audio Port
          3. 10.2.1.4.3Bootstrap Capacitors
          4. 10.2.1.4.4Output Reconstruction Filter
        5. 10.2.1.5Application Curves
      2. 10.2.2PBTL Application
        1. 10.2.2.1Design Requirements
          1. 10.2.2.1.1Detailed Design Procedure
        2. 10.2.2.2Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1Layout Guidelines
      1. 12.1.1Electrical Connection of Thermal pad and Heat Sink
      2. 12.1.2EMI Considerations
      3. 12.1.3General Guidelines
    2. 12.2Layout Example
    3. 12.3Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1Documentation Support
      1. 13.1.1Related Documentation
    2. 13.2Receiving Notification of Documentation Updates
    3. 13.3Community Resources
    4. 13.4Trademarks
    5. 13.5Electrostatic Discharge Caution
    6. 13.6Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Specifications

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)
MINMAXUNIT
PVDD, VBAT DC supply voltage relative to GND –0.3 30 V
VMAX Transient supply voltage: PVDD, VBAT t ≤ 400 ms exposure–1 40V
VRAMP Supply-voltage ramp rate: PVDD, VBAT 75V/ms
VDDDC supply voltage relative to GND–0.3 3.5V
IMAX Maximum current per pin (PVDD, VBAT, OUT_xP, OUT_xM, GND) 8A
IMAX_PULSED Pulsed supply current per PVDD pin (one shot) t < 100 ms12A
VLOGIC Input voltage for logic pins (SCL, SDA, SDIN1, SDIN2, MCLK, BCLK, LRCLK, MUTE, STANDBY, I2C_ADDRx) –0.3 VDD + 0.5V
VGND Maximum voltage between GND pins–0.30.3V
TJ Maximum operating junction temperature–55 150°C
Tstg Storage temperature–55 150°C

ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman-body model (HBM), per AEC Q100–002(1)±3000V
Charged-device model (CDM), per AEC Q100–011All pins±500
Corner pins (1, 28, 29 and 56)±1000
AEC Q100–002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS–001 specification.

Recommended Operating Conditions

MINNOMMAXUNIT
PVDD Output FET supply voltage Relative to GND4.5 26.4 V
VBAT Battery supply voltage inputRelative to GND4.514.418V
VDDDC logic supplyRelative to GND3.03.33.5V
TA Ambient temperature–40125°C
TJ Junction temperatureAn adequate thermal design is required –40150°C
RL Nominal speaker load impedance BTL Mode24Ω
PBTL Mode12
RPU_I2C I2C pullup resistance on SDA and SCL pins14.710
CBypass External capacitance on bypass pinsPin 2, 3, 5, 6, 8, 9, 10, 191µF
COUT External capacitance to GND on OUT pinsLimit set by DC-diagnostic timing13.3µF
LO Output filter inductanceMinimum inductance at ISD current levels1µH

Thermal Information

THERMAL METRIC(1)TAS6424-Q1(2) TAS6424-Q1(3) UNIT
DKQ (HSSOP)DKQ (HSSOP)
56 PINS56 PINS
RθJAJunction-to-ambient thermal resistance °C/W
RθJC(top)Junction-to-case (top) thermal resistance 0.71.1°C/W
RθJBJunction-to-board thermal resistance °C/W
ψJTJunction-to-top characterization parameter °C/W
ψJBJunction-to-board characterization parameter 1010°C/W
RθJC(bot)Junction-to-case (bottom) thermal resistance °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).
JEDEC Standard 4 Layer PCB.
Measured using the TAS6424-Q1 EVM layout and heat sink. The device is not intended to be used without a heat sink.

Electrical Characteristics

Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒ = 1 kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings, see Figure 79 and Figure 82
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
OPERATING CURRENT
IPVDD_IDLE PVDD idle currentAll channels playing, no audio input7590mA
IVBAT_IDLE VBAT idle currentAll channels playing, no audio input90100mA
IPVDD_STBY PVDD standby currentSTANDBYActive, VDD = 0 V110μA
IVBAT_STBY VBAT standby current STANDBYActive, VDD = 0 V410μA
IVDD VDD supply currentAll channels playing, –60-dB signal1518mA
OUTPUT POWER
PO_BTL Output power per channel, BTL4 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C2022W
4 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C2527
2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C3840
2 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C4245
4 Ω, PVDD = 25 V, THD+N = 1%, TC = 75°C5055
4 Ω, PVDD = 25 V, THD+N = 10%, TC = 75°C7075
PO_PBTL Output power per channel in parallel mode, PBTL2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C3540W
2 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C4550
1 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C7280
1 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C8090
2 Ω, PVDD = 25 V, THD+N = 1%, TC = 75°C98120
2 Ω, PVDD = 25 V, THD+N = 10%, TC = 75°C138150
EFFP Power efficiency4 channels operating, 25-W output power/ch 4-Ω load, PVDD = 14.4 V, TC = 25°C, including indcutor losses(1)86%
AUDIO PERFORMANCE
Vn Output noise voltageZero input, A-weighting, gain level 1, PVDD = 14.4 V42μV
Zero input, A-weighting, gain level 2, PVDD = 14.4 V55
Zero input, A-weighting, gain level 3, PVDD = 18 V67
Zero input, A-weighting, gain level 4, PVDD = 25 V85
GAIN Peak output voltage/dBFSGain level 1, Register 0x01, bit 1-0 = 007.5V/FS
Gain level 2, Register 0x01, bit 1-0 = 0115
Gain level 3, Register 0x01, bit 1-0 = 1021
Gain level 4, Register 0x01, bit 1-0 = 1129
Crosstalk Channel crosstalkPVDD = 14.4 Vdc + 1 VRMS, ƒ = 1 kHz –90–75dB
PSRR Power-supply rejection ratio PVDD = 14.4 Vdc + 1 VRMS, ƒ = 1 kHz75dB
THD+NTotal harmonic distortion + noise 0.02%0.05%
GCH Channel-to-channel gain variation–0.500.5dB
LINE OUTPUT PERFORMANCE
Vn_LINEOUT LINE output noise voltageZero input, A-weighting, channel set to LINE MODE42μV
VO_LINEOUT LINE output voltage0-dB input, channel set to LINE MODE5.5VRMS
THD+NLine output total harmonic distortion + noiseVO = 2 VRMS , channel set to LINE MODE 0.01%0.03%
DIGITAL INPUT PINS
VIH Input logic level high70%VDD
VIL Input logic level low30%VDD
IIH Input logic current, highVI = VDD15µA
IIL Input logic current, lowVI = 0–15µA
PWM OUTPUT STAGE
RDS(on) FET drain-to-source resistanceNot including bond wire and package resistance90
OVERVOLTAGE (OV) PROTECTION
VPVDD_OVPVDD overvoltage shutdown27.0 27.828.8 V
VPVDD_OV_HYS PVDD overvoltage shutdown hysteresis0.8V
VVBAT_OVVBAT overvoltage shutdown19.32022V
VVBAT_OV_HYS VBAT overvoltage shutdown hysteresis0.6V
UNDERVOLTAGE (UV) PROTECTION
VBATUV VBAT undervoltage shutdown44.5V
VBATUV_HYS VBAT undervoltage shutdown hysteresis0.2V
PVDDUV PVDD undervoltage shutdown44.5V
PVDDUV_HYS PVDD undervoltage shutdown hysteresis0.2V
BYPASS VOLTAGES
VGVDDGate drive bypass pin voltage7V
VAVDDAnalog bypass pin voltage6V
VVCOMCommon bypass pin voltage2.5V
VVREGRegulator bypass pin voltage5.5V
POWER-ON RESET (POR)
VPOR VDD voltage for POR2.12.7V
VPOR_HY VDD POR recovery hysteresis voltage0.5V
OVERTEMPERATURE (OT) PROTECTION
OTW(i)Channel overtemperature warning150°C
OTSD(i)Channel overtemperature shutdown175°C
OTWGlobal junction overtemperature warningSet by register 0x01 bit 5-6, default value130°C
OTSDGlobal junction overtemperature shutdown160°C
OTHYSOvertemperature hysteresis15°C
LOAD OVER CURRENT PROTECTION
ILIM Overcurrent cycle-by-cycle limitOC Level 144.8A
OC Level 266.5
ISD Overcurrent shutdown OC Level 1, Any short to supply, ground, or other channels7A
OC Level 2, Any short to supply, ground, or other channels9
MUTE MODE
GMUTE Output attenuation100dB
CLICK AND POP
VCP Output click and pop voltageITU-R 2k filter, High-Z/MUTE to Play, Play to Mute/High-Z 7mV
DC OFSET
VOFFSET Output offset voltage25mV
DC DETECT
DCFAULT Output DC fault protection22.5V
DIGITAL OUTPUT PINS
VOH Output voltage for logic level highI = ±2 mA90%VDD
VOL Output voltage for logic level lowI = ±2 mA10%VDD
tDELAY_CLIPDET Signal delay when output clipping detected20μs
LOAD DIAGNOSTICS
S2P Maximum resistance to detect a short from OUT pins to PVDD500Ω
S2GMaximum resistance to detect a short from OUT pins to ground200Ω
SL Shorted load detection toleranceOther channels in Hi-Z±0.5Ω
OLOpen loadOther channels in Hi-Z4070Ω
TDC_DIAGDC diagnostic timeAll 4 Channels230ms
LOLine output6
TLINE_DIAGLine output diagnostic time40ms
ACIMPAC impedance accuracyGain linearity, ƒ = 19 kHz, RL = 2 Ω to 16 Ω, 25%
Offset ±0.5Ω
TAC_DIAGAC diagnostic timeAll 4 Channels520ms
I2C_ADDR PINS
tI2C_ADDR Time delay needed for I2C address set-up 300μs
  1. Tested with Output Inductor DFEG7030D-3R3M.

Timing Requirements

Test conditions (unless otherwise noted): TC = 25 °C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, PO = 1 W/ch, ƒ = 1 kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings, see Figure 79 and Figure 82
MINTYPMAXUNIT
I2C CONTROL PORT (See Figure 42)
tBUS Bus free time between start and stop conditions1.3μs
tHOLD1Hold time, SCL to SDA0ns
tHOLD2Hold time, start condition to SCL0.6μs
tSTART I2C startup time after VDD power on reset12ms
tRISE Rise time, SCL and SDA300ns
tFALLFall time, SCL and SDA300ns
tSU1 Setup, SDA to SCL100ns
tSU2 Setup, SCL to start condition0.6μs
tSU3 Setup, SCL to stop condition0.6μs
tW(H)Required pulse duration SCL High0.6μs
tW(L)Required pulse duration SCL Low1.3μs
SERIAL AUDIO PORT (See Figure 36)
DMCLK, DSCLK Allowable input clock duty cycle45%50%55%
ƒMCLK Supported MCLK frequencies: 128, 256, or 512128512xFS
ƒMCLK_Max Maximum frequency25MHz
tSCY SCLK pulse cycle time40ns
tSCL SCLK pulse-with LOW16ns
tSCH SCLK pulse-with HIGH16ns
trise/fall Rise and fall time4ns
tSF SCLK rising edge to FSYNC edge8ns
tFS FSYNC rising edge to SCLK edge8ns
tDS DATA set-up time8ns
tDH DATA hold time8ns
ci Input capacitance, pins MCLK, SCLK, FSYNC, SDIN1, SDIN210pF
TLALatency from input to output measured in FSYNC sample countFSYNC = 44.1 kHz or 48 kHz30
FSYNC = 96 kHz12

Typical Characteristics

TA = 25 ºC, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.11 MHz, AES17 filter, default I2C settings, see Figure 79 and Figure 82 (unless otherwise noted)
TAS6424-Q1 D002_SLOS870.gif
PO = 1 W
Figure 1. Crosstalk vs Frequency
TAS6424-Q1 D024_SLOS870.gif
PO = 1 W
Figure 3. VBAT PSRR vs Frequency
TAS6424-Q1 D006_SLOS870.gif
PO = 1 W 2.11-MHz fSW
Figure 5. THD+N vs Frequency
TAS6424-Q1 D008_SLOS870.gif
PO = 1 W 24 V 2.11-MHz fSW
Figure 7. THD+N vs Frequency
TAS6424-Q1 D010_SLOS870.gif
2.11-MHz fSW
Figure 9. THD+N vs Power
TAS6424-Q1 D012_SLOS870.gif
24 V2.11-MHz fSW
Figure 11. THD+N vs Power
TAS6424-Q1 D014_SLOS870.gif
10% THD 2.11-MHz fSW
Figure 13. Output Power vs Supply Voltage
TAS6424-Q1 D016_SLOS870.gif
A-weighted Noise 2.11-MHz fSW
Figure 15. Noise vs Supply voltage
TAS6424-Q1 D020_SLOS870.gif
4 Ω 2.1-MHz fSW
Figure 17. Power Efficiency vs Output Power
TAS6424-Q1 D018_SLOS870.gif
2 Ω 2.1-MHz fSW
Figure 19. Power Efficiency vs Output Power
TAS6424-Q1 D026_SLOS870.gif
Figure 21. VBAT Current vs Voltage
TAS6424-Q1 D028_SLOS870.gif
1 W 384-kHz fSW
Figure 23. PBTL THD+N vs Frequency
TAS6424-Q1 D030_SLOS870.gif
PO = 1 W 384-kHz fSW24-V PVDD
Figure 25. PBTL THD+N vs Frequency
TAS6424-Q1 D032_SLOS870.gif
384-kHz fSW
Figure 27. PBTL THD+N vs Power
TAS6424-Q1 D034_SLOS870.gif
384-kHz fSW
Figure 29. PBTL THD+N vs Power
TAS6424-Q1 D036_SLOS870.gif
384-kHz fSW
Figure 31. Output Power vs Voltage
TAS6424-Q1 D038_SLOS870.gif
384-kHz fSW
Figure 33. Power Dissipation vs Output Power
TAS6424-Q1 D022_SLOS870.gif
PO = 1 W
Figure 2. PVDD PSRR vs Frequency
TAS6424-Q1 D005_SLOS870.gif
PO = 1 W 384-kHz fSW
Figure 4. THD+N vs Frequency
TAS6424-Q1 D007_SLOS870.gif
PO = 1 W 24 V384-kHz fSW
Figure 6. THD+N vs Frequency
TAS6424-Q1 D009_SLOS870.gif
384-kHz fSW
Figure 8. THD+N vs Power
TAS6424-Q1 D011_SLOS870.gif
24 V 384-kHz fSW
Figure 10. THD+N vs Power
TAS6424-Q1 D013_SLOS870.gif
10% THD384-kHz fSW
Figure 12. Output Power vs Supply Voltage
TAS6424-Q1 D015_SLOS870.gif
A-weighted Noise 384-kHz fSW
Figure 14. Noise vs Supply Voltage
TAS6424-Q1 D019_SLOS870.gif
4 Ω 384-kHz fSW
Figure 16. Power Efficiency vs Output Power
TAS6424-Q1 D017_SLOS870.gif
2 Ω 384-kHz fSW
Figure 18. Power Efficiency vs Output Power
TAS6424-Q1 D025_SLOS870.gif
Figure 20. PVDD Current vs Voltage
TAS6424-Q1 D027_SLOS870.gif
Figure 22. PVDD Standby Current vs Voltage
TAS6424-Q1 D029_SLOS870.gif
PO = 1 W 2.1-MHz fSW
Figure 24. PBTL THD+N vs Frequency
TAS6424-Q1 D031_SLOS870.gif
Po = 1 W 2.1-MHz fSW24-V PVDD
Figure 26. PBTL THD+N vs Frequency
TAS6424-Q1 D033_SLOS870.gif
2.1-MHz fSW
Figure 28. PBTL THD+N vs Power
TAS6424-Q1 D035_SLOS870.gif
2.1-MHz fSW24-V PVDD
Figure 30. PBTL THD+N vs Power
TAS6424-Q1 D037_SLOS870.gif
2.1-MH fSW
Figure 32. Output Power vs Voltage
TAS6424-Q1 D039_SLOS870.gif
2.1-MHz fSW
Figure 34. Power Dissipation vs Output Power