TCI6630K2L Multicore DSP+ARM KeyStone II System-on-Chip (SoC) |


Multicore DSP+ARM KeyStone II System-on-Chip (SoC)


The TCI6630K2L Communications Infrastructure KeyStone SoC is a member of the C66x family based on TI’s new KeyStone II Multicore SoC Architecture and is a low-power baseband solution with integrated digital front end (DFE) that meets the more stringent power, size, and cost requirements of small cell wireless base stations. In enterprise and pico base stations, the device’s ARM and DSP cores deliver exceptional processing power on platforms for developing all wireless standards including WCDMA/HSPA/HSPA+, TD-SCDMA, GSM, TDD-LTE, FDD-LTE, and WiMAX.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (ARM CorePac, C66x CorePacs, IP network, radio layers 1, 2, and 3, and transport processing) and uses a queue-based communication system that allows the SoC resources to operate efficiently and seamlessly. This unique SoC architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to dedicated coprocessors and high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The addition of the ARM CorePac in the TCI6630 enables the ability for layer 2 and layer 3 processing on-chip. Operations such as Traffic Control, Local O&M, NBAP/FP termination, and SCTP processing can all be performed with the Cortex-A15 processor.

TI’s new C66x core launches a new era of DSP technology by combining fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x CorePac incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing. These enhancements yield tremendous performance improvements in multi-antenna 4.8G signal processing for algorithms like MIMO and beamforming.

The TCI6630K2L contains many wireless basestation coprocessors to offload the bulk of the processing demands of layer 1 and layer 2 basestation processing. This keeps the cores free for receiver algorithms and other differentiating functions. The SoC contains multiple copies of key coprocessors such as the FFTC and TCP3d. A key coprocessor for enabling high data rates is the Bit Rate Coprocessor (BCP), which handles the entire downlink bit-processing chain and much of the receive bit processing. The architectural elements of the SoC (Multicore Navigator) ensure that all the bits are processed without any CPU intervention or overhead, allowing the system to make optimal use of its resources.

TI’s scalable multicore SoC architecture solutions provide developers with a range of software-compatible and hardware-compatible devices to minimize development time and maximize reuse across all basestation platforms from Femto to Macro.

The TCI6630K2L device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.


  • Four TMS320C66x DSP Core Subsystems (C66x
    CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed/Floating-Point
      DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2 GHz
    • Memory
      • 32K Byte L1P Per CorePac
      • 32K Byte L1D Per CorePac
      • 1024K Byte Local L2 Per CorePac
  • ARM CorePac
    • Two ARM® Cortex®-A15 MPCore™ Processors
      at Up to 1.2 GHz
    • 1MB L2 Cache Memory Shared by Two ARM
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC for Low
      Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory Shared by Four DSP
      CorePacs and One ARM CorePac
    • Memory Protection Unit for Both MSM SRAM
      and DDR3_EMIF
  • On-chip Standalone RAM (OSR) - 1MB On-Chip
    SRAM for Additional Shared Memory
  • Hardware Coprocessors
    • Two Turbo Decoders
      • Supports WCDMA/HSPA/HSPA+/TD-
        SCDMA, LTE, LTE-A and WiMAX
      • Supports Up to 282 Mbps for LTE at Block
        Size 6144, 8 Iterations and Up to 206 Mbps
        for WCDMA at Block Size 5114, 8 Iterations
      • Low DSP Overhead – HW Interleaver Table
        Generation and CRC Check
    • Four Viterbi Decoders
      • Supports Up to 50 Mbps (Length 9, Rate 1/3,
        Block Size 2500)
    • One WCDMA Receive Acceleration
      • Supports Up to 8192 Correlators
    • WCDMA Transmit Acceleration Coprocessor
      • Supports Up to 2304 Spreaders
    • Two Fast Fourier Transform Coprocessors
      • Support Up to 1200 Mscps at FFT Size 1024
    • Bit Rate Coprocessor
        and WiMAX Uplink and Downlink Bit
      • Includes Encoding, Rate
        Matching/Dematching, Segmentation,
        Multiplexing, and More
      • Supports Up to DL 1525 Mbps and UL 1030
        Mbsp for LTE and DL 784 Mbps and UL 216
        Mbsp for WCDMA/TD-SCDMA
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
    • Packet-Based DMA for Zero-Overhead
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5, ZUC, ZUC-MAC
      • Up to 6.4 Gbps IPSec and 3 Gbps Air Ciphering
    • Ethernet Subsystem
      • Four SGMII Port Switch
  • Eight Rake/Search Accelerators (RSA) for
    • Chip Rate Processing for WCDMA Rel’99,
      HSDPA, and HSDPA+
    • Reed-Muller Decoding
  • Peripherals
    • Digital Front End (DFE) Subsystem
      • Support up to Four Lane JESD204A/B (7.37
        Gbps Line Rate Max.) Interface to Multiple
        Data Converters
      • Integration of Digital Down/Up-Conversion
        (DDC/DUC), Crest Factor Reduction (CFR),
        and Digital Pre-Distortion (DPD) Modules
    • IQNet Subsystem
      • Transporting baseband antenna streams
        over two-lane SerDes-based Antenna
        Interface Link (AIL)
      • Transporting baseband antenna streams to
        an integrated Digital Front End (DFE)
      • Operating at Up to 9.83 Gbps
      • Compliant with OBSAI RP3 and CPRI
        Standards for 3G / 4G (WCDMA, LTE TDD,
        LTE FDD, TD-SCDMA, and WiMAX)
    • Two One-Lane PCIe Gen2 Interfaces
      • Supports Up to 5 GBaud
    • Three Enhanced Direct Memory Access (EDMA)
    • 72-Bit DDR3 Interface, Speeds Up to 1600 MHz
    • EMIF16 Interface
    • USB 3.0 Interface
    • USIM Interface
    • Four UART Interfaces
    • Three I2C Interfaces
    • 64 GPIO Pins
    • Three SPI Interfaces
    • Semaphore Module
    • Fourteen 64-Bit Timers
  • Commercial Case Temperature:
    • 0°C to 100°C
  • Extended Case Temperature:
    • –40°C to 100°C