SNAS647D February   2015  – March 2016 TDC7200

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Companion Device
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 LDO
      2. 8.3.2 CLOCK
      3. 8.3.3 Counters
        1. 8.3.3.1 Coarse and Clock Counters Description
        2. 8.3.3.2 Coarse and Clock Counters Overflow
        3. 8.3.3.3 Clock Counter STOP Mask
        4. 8.3.3.4 ENABLE
    4. 8.4 Device Functional Modes
      1. 8.4.1 Calibration
      2. 8.4.2 Measurement Modes
        1. 8.4.2.1 Measurement Mode 1
          1. 8.4.2.1.1 Calculating Time-of-Flight (Measurement Mode 1)
        2. 8.4.2.2 Measurement Mode 2
          1. 8.4.2.2.1 Calculating Time-of-Flight (TOF) (Measurement Mode 2)
      3. 8.4.3 Timeout
      4. 8.4.4 Multi-Cycle Averaging
      5. 8.4.5 START and STOP Edge Polarity
      6. 8.4.6 Measurement Sequence
      7. 8.4.7 Wait Times for TDC7200 Startup
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI)
        1. 8.5.1.1 CSB
        2. 8.5.1.2 SCLK
        3. 8.5.1.3 DIN
        4. 8.5.1.4 DOUT
        5. 8.5.1.5 Register Read/Write
        6. 8.5.1.6 Auto Increment Mode
    6. 8.6 Register Maps
      1. 8.6.1  Register Initialization
      2. 8.6.2  CONFIG1: Configuration Register 1 R/W (address = 00h) [reset = 0h]
      3. 8.6.3  CONFIG2: Configuration Register 2 R/W (address = 01h) [reset = 40h]
      4. 8.6.4  INT_STATUS: Interrupt Status Register (address = 02h) [reset = 00h]
      5. 8.6.5  INT_MASK: Interrupt Mask Register R/W (address = 03h) [reset = 07h]
      6. 8.6.6  COARSE_CNTR_OVF_H: Coarse Counter Overflow High Value Register (address = 04h) [reset = FFh]
      7. 8.6.7  COARSE_CNTR_OVF_L: Coarse Counter Overflow Low Value Register (address = 05h) [reset = FFh ]
      8. 8.6.8  CLOCK_CNTR_OVF_H: Clock Counter Overflow High Register (address = 06h) [reset = FFh]
      9. 8.6.9  CLOCK_CNTR_OVF_L: Clock Counter Overflow Low Register (address = 07h) [reset = FFh]
      10. 8.6.10 CLOCK_CNTR_STOP_MASK_H: CLOCK Counter STOP Mask High Value Register (address = 08h) [reset = 00h]
      11. 8.6.11 CLOCK_CNTR_STOP_MASK_L: CLOCK Counter STOP Mask Low Value Register (address = 09h) [reset = 00h]
      12. 8.6.12 TIME1: Time 1 Register (address: 10h) [reset = 00_0000h]
      13. 8.6.13 CLOCK_COUNT1: Clock Count Register (address: 11h) [reset = 00_0000h]
      14. 8.6.14 TIME2: Time 2 Register (address: 12h) [reset = 00_0000h]
      15. 8.6.15 CLOCK_COUNT2: Clock Count Register (address: 13h) [reset = 00_0000h]
      16. 8.6.16 TIME3: Time 3 Register (address: 14h) [reset = 00_0000h]
      17. 8.6.17 CLOCK_COUNT3: Clock Count Registers (address: 15h) [reset = 00_0000h]
      18. 8.6.18 TIME4: Time 4 Register (address: 16h) [reset = 00_0000h]
      19. 8.6.19 CLOCK_COUNT4: Clock Count Register (address: 17h) [reset = 00_0000h]
      20. 8.6.20 TIME5: Time 5 Register (address: 18h) [reset = 00_0000h]
      21. 8.6.21 CLOCK_COUNT5: Clock Count Register (address: 19h) [reset = 00_0000h]
      22. 8.6.22 TIME6: Time 6 Register (address: 1Ah) [reset = 00_0000h]
      23. 8.6.23 CALIBRATION1: Calibration 1 Register (address: 1Bh ) [reset = 00_0000h]
      24. 8.6.24 CALIBRATION2: Calibration 2 Register (address: 1Ch ) [reset = 00_0000h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Flow Meter Regulations and Accuracy
        2. 9.2.2.2 Transmit Time in Ultrasonic Flow Meters
        3. 9.2.2.3 ΔTOF Accuracy Requirement Calculation
      3. 9.2.3 Application Curves
    3. 9.3 Post Filtering Recommendations
    4. 9.4 CLOCK Recommendations
      1. 9.4.1 CLOCK Accuracy
      2. 9.4.2 CLOCK Jitter
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Power Supply Recommendations

The analog circuitry of the TDC7200 is designed to operate from an input voltage supply range between 2 V and 3.6 V. It is recommended to place a 100 nF ceramic bypass capacitor to ground as close as possible to the VDD pins. In addition, an electrolytic or tantalum capacitor with value greater than 1 µF is recommended. The bulk capacitor does not need to be in close vicinity with the TDC7200 and could be close to the voltage source terminals or at the output of the voltage regulators powering the TDC7200.