THS10064 10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low Power | TI.com

THS10064 (ACTIVE) 10-Bit, 6 MSPS ADC Quad Ch. (Config.), DSP/uP Interface, Integ. 16x FIFO, Ch. AutoScan, Low Power

 

Description

The THS10064 is a CMOS, low-power, 10-bit, 6 MSPS analog-to-digital converter (ADC). The speed, resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Internal control registers are used to program the ADC into the desired mode. The THS10064 consists of four analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured to single-ended or differential inputs. An integrated 16 word deep FIFO allows the storage of data in order to improve data transfers to the processor. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided.

An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. Two different conversion modes can be selected. In single conversion mode, a single and simultaneous conversion of up to four inputs can be initiated by using the single conversion start signal (CONVST)\. The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. In continuous conversion mode, an external clock signal is applied to the CONV_CLK input of the THS10064. The internal clock oscillator is switched off in continuous conversion mode.

The THS10064C is characterized for operation from 0°C to 70°C, and the THS10064I is characterized for operation from –40°C to 85°C.

Features

  • High-Speed 6 MSPS ADC
  • 4 Analog Inputs
  • Simultaneous Sampling of 4 Single-Ended Signals or 2 Differential Signals or Combination of Both
  • Differential Nonlinearity Error: ±1 LSB
  • Integral Nonlinearity Error: ±1.5 LSB
  • Signal-to-Noise and Distortion Ratio: 59 dB at fI = 2 MHz
  • Auto-Scan Mode for 2, 3, or 4 Inputs
  • 3-V or 5-V Digital Interface Compatible
  • Low Power: 216 mW Max
  • 5-V Analog Single Supply Operation
  • Internal Voltage References ...50 PPM/°C and ±5% Accuracy
  • Glueless DSP Interface
  • Parallel µC/DSP Interface
  • Integrated FIFO
  • Available in TSSOP Package
  • Pin Compatible With 12-Bit THS1206
  • APPLICATIONS
    • Radar Applications
    • Communications
    • Control Applications
    • High-Speed DSP Front-End
    • Automotive Applications

WEBENCH® Designer THS10064



Parametrics

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Part number Order Resolution (Bits) Sample rate (Max) (kSPS) Number of input channels Interface Operating temperature range (C) Package Group Approx. price (US$) Power consumption (Typ) (mW) Package size: mm2:W x L (PKG) Architecture Input type Multi-channel configuration Reference mode Features Input range (Max) (V) Input range (Min) (V) Analog voltage AVDD (Min) (V) Analog voltage AVDD (Max) (V) Digital supply (Min) (V) Digital supply (Max) (V) INL (Max) (+/-LSB) SNR (dB) THD (Typ) (dB) Rating
THS10064 Order now 10     6000     4     Parallel     -40 to 85
0 to 70    
TSSOP | 32     6.46 | 1ku     186     32TSSOP: 89 mm2: 8.1 x 11 (TSSOP | 32)     Pipeline     Differential
Single-Ended    
Multiplexed     Ext
Int    
    4     1.4     4.75     5.25     3     5.25     1     61     -64     Catalog