The THS10064 is a CMOS, low-power, 10-bit, 6 MSPS analog-to-digital converter (ADC). The speed, resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error correction logic provides for no missing codes over the full operating temperature range. Internal control registers are used to program the ADC into the desired mode. The THS10064 consists of four analog inputs, which are sampled simultaneously. These inputs can be selected individually and configured to single-ended or differential inputs. An integrated 16 word deep FIFO allows the storage of data in order to improve data transfers to the processor. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided.
An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. Two different conversion modes can be selected. In single conversion mode, a single and simultaneous conversion of up to four inputs can be initiated by using the single conversion start signal (CONVST)\. The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. In continuous conversion mode, an external clock signal is applied to the CONV_CLK input of the THS10064. The internal clock oscillator is switched off in continuous conversion mode.
The THS10064C is characterized for operation from 0°C to 70°C, and the THS10064I is characterized for operation from 40°C to 85°C.
|Sample Rate (Max) (kSPS)|
|Number of input channels|
|Operating temperature range (C)|
|Approx. price (US$)|
|Power consumption (Typ) (mW)|
|Package size: mm2:W x L (PKG)|
|Input range (Max) (V)|
|Input range (Min) (V)|
|Analog voltage AVDD (Min) (V)|
|Analog voltage AVDD (Max) (V)|
|Digital supply (Min) (V)|
|Digital supply (Max) (V)|
|INL (Max) (+/-LSB)|
|THD (Typ) (dB)|
-40 to 85
0 to 70
|TSSOP | 32|
|5.72 | 1ku|
|32TSSOP: 89 mm2: 8.1 x 11 (TSSOP | 32)|