SLOS930A November 2015  – November 2015 THS4541-Q1

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Family Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5 Electrical Characteristics: (Vs+) - Vs- = 5 V
    6. 7.6 Electrical Characteristics: (Vs+) - Vs- = 3 V
    7. 7.7Typical Characteristics
      1. 7.7.15-V Single Supply
      2. 7.7.23-V Single Supply
      3. 7.7.33-V to 5-V Supply Range
  8. Parameter Measurement Information
    1. 8.1Example Characterization Circuits
    2. 8.2Frequency-Response Shape Factors
    3. 8.3I/O Headroom Considerations
    4. 8.4Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    5. 8.5Noise Analysis
    6. 8.6Factors Influencing Harmonic Distortion
    7. 8.7Driving Capacitive Loads
    8. 8.8Thermal Analysis
  9. Detailed Description
    1. 9.1Overview
      1. 9.1.1Terminology and Application Assumptions
    2. 9.2Functional Block Diagram
    3. 9.3Feature Description
      1. 9.3.1Differential I/O
      2. 9.3.2Power-Down Control Pin (PD)
        1. 9.3.2.1Operating the Power Shutdown Feature
      3. 9.3.3Input Overdrive Operation
    4. 9.4Device Functional Modes
      1. 9.4.1Operation from Single-Ended Sources to Differential Outputs
        1. 9.4.1.1AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
        2. 9.4.1.2DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
        3. 9.4.1.3Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA
        4. 9.4.1.4Input Impedance for the Single-Ended to Differential FDA Configuration
      2. 9.4.2Differential-Input to Differential-Output Operation
        1. 9.4.2.1AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 9.4.2.2DC-Coupled, Differential-Input to Differential-Output Design Issues
  10. 10Application and Implementation
    1. 10.1Application Information
    2. 10.2Typical Applications
      1. 10.2.1Designing Attenuators
        1. 10.2.1.1Design Requirements
        2. 10.2.1.2Detailed Design Procedure
        3. 10.2.1.3Application Curve
      2. 10.2.2Interfacing to High-Performance ADCs
        1. 10.2.2.1Design Requirements
        2. 10.2.2.2Detailed Design Procedure
        3. 10.2.2.3Application Curve
  11. 11Power-Supply Recommendations
  12. 12Layout
    1. 12.1Layout Guidelines
    2. 12.2Layout Example
  13. 13Device and Documentation Support
    1. 13.1Device Support
      1. 13.1.1Development Support
        1. 13.1.1.1TINA Simulation Model Features
    2. 13.2Documentation Support
      1. 13.2.1Related Documentation
    3. 13.3Community Resource
    4. 13.4Trademarks
    5. 13.5Electrostatic Discharge Caution
    6. 13.6Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information

1 Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range
    • Device HBM Classification Level 2
    • Device CDM Classification Level C6
  • Fully Differential Amplifier (FDA) Architecture
  • Bandwidth: 500 MHz (G = 2 V/V)
  • Gain Bandwidth Product: 850 MHz
  • Slew Rate: 1500 V/µs
  • HD2: –95 dBc at 10 MHz (2 VPP, RL = 500 Ω)
  • HD3: –90 dBc at 10 MHz (2 VPP, RL = 500 Ω)
  • Input Voltage Noise: 2.2 nV/Hz (f > 100 kHz)
  • Low offset drift: ±0.5 µV/°C (typ)
  • Negative Rail Input (NRI)
  • Rail-to-Rail Output (RRO)
  • Robust Operation for Rload ≥ 50 Ω
  • Output Common-Mode Control
  • Power Supply:
    • Single-Supply Voltage Range: 2.7 V to 5.4 V
    • Split-Supply Voltage Range: ±1.35 V to ±2.7 V
    • Quiescent Current: 10.1 mA (5-V Supply)
  • Power-Down Capability: 2 µA (typ)

2 Applications

  • Low-Power, High-Performance ADC Driver
    • SAR, ΔΣ, and Pipeline
  • Low Power, High Performance (DC or AC Coupled)
    • Single-Ended to Differential Amplifier
    • Differential to Differential Amplifier
  • Differential Active Filters
  • Differential Transimpedance for DAC Outputs
  • DC- or AC-Coupled Interface to the ADC3xxx Family of Low-Power, High-Performance ADCs
  • Pin-Compatible to ADA4932-1 (VQFN-16)

3 Description

The THS4541-Q1 device is a low-power, voltage-feedback, fully differential amplifier (FDA) with an input common-mode range below the negative rail, and rail-to-rail output. Designed for low-power data acquisition systems where high density is critical in a high-performance analog-to-digital converter (ADC) or digital-to-analog converter (DAC) interface design.

The THS4541-Q1 device features the negative-rail input required when interfacing a DC-coupled, ground-centered, source signal. This negative-rail input, with rail-to-rail output, allows for easy interface between single-ended, ground-referenced, bipolar signal sources and a wide variety of successive approximation register (SAR), delta-sigma (ΔΣ), or pipeline ADCs using only a single 2.7-V to 5.4-V power supply.

The THS4541-Q1 device is characterized for operation over the wide temperature range of –40°C to +125°C available in a 16-pin VQFN package.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
THS4541-Q1VQFN (16)3.00 mm × 3.00 mm
  1. For all available packages, see the package option addendum at the end of the data sheet.

Simplified Schematic

THS4541-Q1 ac_coupled_gain_los375.gif

Single to Differential Gain of 2, 2-VPP Output

THS4541-Q1 D013_SLOS375.gif