(ACTIVE) Low-Noise JFET-Input General-Purpose Operational Amplifier


Functional Diagram


The TL07xx JFET-input operational amplifiers incorporate well-matched, high-voltage JFET and bipolar transistors in a monolithic integrated circuit. The devices feature high slew rates, low-input bias and offset currents, and low offset-voltage temperature coefficient. The low harmonic distortion and low noise make the TL07x series ideally suited for high-fidelity and audio pre-amplifier applications. The TL071 device has offset pins to support external input offset correction.


  • Low Power Consumption
  • Wide Common-Mode and Differential Voltage Ranges
  • Low Input Bias and Offset Currents
  • Output Short-Circuit Protection
  • Low Total Harmonic Distortion: 0.003% (Typical)
  • Low Noise
    Vn = 18 nV/√Hz (Typical) at f = 1 kHz
  • High-Input Impedance: JFET Input Stage
  • Internal Frequency Compensation
  • Latch-Up-Free Operation
  • High Slew Rate: 13 V/µs (Typical)
  • Common-Mode Input Voltage Range
    Includes VCC+

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Number of Channels (#) 1    
Total Supply Voltage (Min) (+5V=5, +/-5V=10) 7    
Total Supply Voltage (Max) (+5V=5, +/-5V=10) 36    
GBW (Typ) (MHz) 3    
Slew Rate (Typ) (V/us) 13    
Rail-to-Rail In to V+    
Vos (Offset Voltage @ 25C) (Max) (mV) 6    
Iq per channel (Typ) (mA) 1.4    
Vn at 1kHz (Typ) (nV/rtHz) 18    
Rating Catalog    
Operating Temperature Range (C) -40 to 85^0 to 70    
Package Group PDIP|8^SOIC|8^SO|8    
Package Size: mm2:W x L (PKG) See datasheet (PDIP)^8SO: 48 mm2: 7.8 x 6.2 (SO|8)^8SOIC: 29 mm2: 6 x 4.9 (SOIC|8)    
Offset Drift (Typ) (uV/C) 18    
Features Standard Amps    
Input Bias Current (Max) (pA) 200    
CMRR (Typ) (dB) 100    
Output Current (Typ) (mA) 10    
Architecture FET    

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Technical Documents

Datasheet (1)

Application notes (3)

More literature (1)

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