(ACTIVE) Dual High Slew Rate JFET-Input Operational Amplifier


Functional Diagram


The TL08xx JFET-input operational amplifier family is designed to offer a wider selection than any previously developed operational amplifier family. Each of these JFET-input operational amplifiers incorporates well-matched, high-voltage JFET and bipolar transistors in a monolithic integrated circuit. The devices feature high slew rates, low input bias and offset currents, and low offset-voltage temperature coefficient.


  • Low Power Consumption: 1.4 mA/ch Typical
  • Wide Common-Mode and Differential Voltage
  • Low Input Bias Current: 30 pA Typical
  • Low Input Offset Current: 5 pA Typical
  • Output Short-Circuit Protection
  • Low Total Harmonic Distortion: 0.003% Typical
  • High Input Impedance: JFET Input Stage
  • Latch-Up-Free Operation
  • High Slew Rate: 13 V/µs Typical
  • Common-Mode Input Voltage Range
    Includes VCC+


Number of Channels (#) 2    
Total Supply Voltage (Min) (+5V=5, +/-5V=10) 7    
Total Supply Voltage (Max) (+5V=5, +/-5V=10) 36    
GBW (Typ) (MHz) 3    
Slew Rate (Typ) (V/us) 13    
Rail-to-Rail In to V+    
Vos (Offset Voltage @ 25C) (Max) (mV) 6    
Iq per channel (Typ) (mA) 1.4    
Vn at 1kHz (Typ) (nV/rtHz) 18    
Rating Catalog    
Operating Temperature Range (C) -40 to 85^0 to 70    
Package Group PDIP|8^SOIC|8^SO|8^TSSOP|8    
Package Size: mm2:W x L (PKG) See datasheet (PDIP)^8SO: 48 mm2: 7.8 x 6.2 (SO|8)^8SOIC: 29 mm2: 6 x 4.9 (SOIC|8)^8TSSOP: 19 mm2: 6.4 x 3 (TSSOP|8)    
Offset Drift (Typ) (uV/C) 18    
Features Standard Amps    
Input Bias Current (Max) (pA) 200    
CMRR (Typ) (dB) 86    
Output Current (Typ) (mA) 10    
Architecture FET    

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Technical Documents

Datasheet (1)

Application notes (2)

More literature (1)

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