The TL16C554 and the TL16C554I are enhanced quadruple versions of the TL16C550B asynchronous communications element (ACE). Each channel performs serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete status of each channel of the quadruple ACE can be read at any time during functional operation by the CPU. The information obtained includes the type and condition of the operation performed and any error conditions encountered.
The TL16C554 and the TL16C554I quadruple ACE can be placed in an alternate FIFO mode, which activates the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system efficiency, all logic is on the chip. Two terminal functions allow signaling of direct memory access (DMA) transfers. Each ACE includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and (216-1).
The TL16C554 and the TL16C554I are available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package and in an 80-pin (TQFP) PN package.
|Part number||Order||Number of channels (#)||FIFOs (bytes)||Rx FIFO trigger levels (#)||Tx FIFO trigger levels (#)||Programmable FIFO trigger levels||CPU interface||Baud rate (max) at Vcc = 1.8 V & with 16X sampling (Mbps)||Baud rate (max) at Vcc = 2.5 V & with 16X sampling (Mbps)||Baud rate (max) at Vcc = 3.3 V & with 16X sampling (Mbps)||Baud rate (max) at Vcc = 5.0 V & with 16X sampling (Mbps)||Operating voltage (V)||Auto RTS/CTS||Rating||Operating temperature range (C)||Package Group|
-40 to 85
0 to 70
LQFP | 80
PLCC | 68