Product details

Function General-purpose timer Iq (typ) (mA) 0.25 Rating Catalog Operating temperature range (°C) to Supply voltage (max) (V) 15 Supply voltage (min) (V) 2
Function General-purpose timer Iq (typ) (mA) 0.25 Rating Catalog Operating temperature range (°C) to Supply voltage (max) (V) 15 Supply voltage (min) (V) 2
DIESALE (TD) See data sheet
  • Very Low Power Consumption
  • Capable of Operation in Astable Mode
  • CMOS Output Capable of Swinging Rail to Rail
  • High Output-Current Capability
  • Output Fully Compatible With CMOS, TTL, and MOS
  • Low Supply Current Reduces Spikes During Output Transitions
  • Single-Supply Operation From 2 V to 15 V
  • Functionally Interchangeable With the NE555; Has Same Pinout
  • ESD Protection Exceeds 2000 V Per
    MIL-STD-883C, Method 3015.2
  • Available in Q-Temp Automotive
    • High Reliability Automotive Applications
    • Configuration Control/Print Support
    • Qualification to Automotive Standards

LinCMOS is a trademark of Texas Instruments.

  • Very Low Power Consumption
  • Capable of Operation in Astable Mode
  • CMOS Output Capable of Swinging Rail to Rail
  • High Output-Current Capability
  • Output Fully Compatible With CMOS, TTL, and MOS
  • Low Supply Current Reduces Spikes During Output Transitions
  • Single-Supply Operation From 2 V to 15 V
  • Functionally Interchangeable With the NE555; Has Same Pinout
  • ESD Protection Exceeds 2000 V Per
    MIL-STD-883C, Method 3015.2
  • Available in Q-Temp Automotive
    • High Reliability Automotive Applications
    • Configuration Control/Print Support
    • Qualification to Automotive Standards

LinCMOS is a trademark of Texas Instruments.

The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS process. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of its high input impedance, this device uses smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power supply voltage.

Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering.

While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC555 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE555.

The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS process. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of its high input impedance, this device uses smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power supply voltage.

Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering.

While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC555 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE555.

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* Data sheet LinCMOS Timer, TLC555-DIE datasheet 25 Jul 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

TLC555 TINA-TI Astable Reference Design (Rev. B)

SLFM002B.TSC (100 KB) - TINA-TI Reference Design
Simulation model

TLC555 TINA-TI Mono Reference Design (Rev. B)

SLFM003B.TSC (102 KB) - TINA-TI Reference Design
Simulation model

TLC555 TINA-TI Spice Model

SLFM005.ZIP (9 KB) - TINA-TI Spice Model
Simulation model

TLC555x and TLC556x PSpice Model (Rev. E)

SLFJ002E.ZIP (25 KB) - PSpice Model
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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