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TLC6C598-Q1

ACTIVE

Automotive power logic 8-bit Shift Register LED driver

Product details

Number of channels 8 Topology Open drain Rating Automotive Operating temperature range (°C) -40 to 125 Vin (min) (V) 3 Vin (max) (V) 5.5 Vout (min) (V) 0 Vout (max) (V) 40 Iout (max) (A) 0.4 Features Thermal shutdown
Number of channels 8 Topology Open drain Rating Automotive Operating temperature range (°C) -40 to 125 Vin (min) (V) 3 Vin (max) (V) 5.5 Vout (min) (V) 0 Vout (max) (V) 40 Iout (max) (A) 0.4 Features Thermal shutdown
SOIC (D) 16 59.4 mm² 9.9 x 6 TSSOP (PW) 16 32 mm² 5 x 6.4
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C3B
  • Wide Vcc From 3 V to 5.5 V
  • Output Maximum Rating of.40 V
  • Eight Power DMOS Transistor Outputs of 50-mA Continuous Current With VCC = 5 V
  • Thermal Shutdown Protection
  • Enhanced Cascading for Multiple Stages
  • All Registers Cleared With Single Input
  • Low Power Consumption
  • Slow Switching Time (tr and tf), Which Helps Significantly With Reducing EMI
  • 16-Pin TSSOP-PW Package
  • 16-Pin SOIC-D Package
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C3B
  • Wide Vcc From 3 V to 5.5 V
  • Output Maximum Rating of.40 V
  • Eight Power DMOS Transistor Outputs of 50-mA Continuous Current With VCC = 5 V
  • Thermal Shutdown Protection
  • Enhanced Cascading for Multiple Stages
  • All Registers Cleared With Single Input
  • Low Power Consumption
  • Slow Switching Time (tr and tf), Which Helps Significantly With Reducing EMI
  • 16-Pin TSSOP-PW Package
  • 16-Pin SOIC-D Package

The TLC6C598-Q1 is a monolithic, medium-voltage, low-current power 8-bit shift register designed for use in systems that require relatively moderate load power, such as LEDs.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shift register clear (CLR) is high. A low on CLR clears all registers in the device. Holding the output enable (G) high, holds all data in the output buffers low, and all drain outputs are off. Holding G low makes data from the storage register transparent to the output buffers. When data in the output buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current capability. The serial output (SER OUT) clocks out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This provides improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference. The device contains built-in thermal shutdown protection.

Outputs are low-side, open-drain DMOS transistors with output ratings of 40 V and 50 mA continuous sink-current capabilities when Vcc = 5 V. The current limit decreases as the junction temperature increases for additional device protection. The device also provides up to 2000 V of ESD protection when tested using the human-body model and 200 V when using the machine model.

The TLC6C598-Q1 characterization is for for operation over the operating ambient temperature range of −40°C to 125°C.

The TLC6C598-Q1 is a monolithic, medium-voltage, low-current power 8-bit shift register designed for use in systems that require relatively moderate load power, such as LEDs.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shift register clear (CLR) is high. A low on CLR clears all registers in the device. Holding the output enable (G) high, holds all data in the output buffers low, and all drain outputs are off. Holding G low makes data from the storage register transparent to the output buffers. When data in the output buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current capability. The serial output (SER OUT) clocks out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This provides improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference. The device contains built-in thermal shutdown protection.

Outputs are low-side, open-drain DMOS transistors with output ratings of 40 V and 50 mA continuous sink-current capabilities when Vcc = 5 V. The current limit decreases as the junction temperature increases for additional device protection. The device also provides up to 2000 V of ESD protection when tested using the human-body model and 200 V when using the machine model.

The TLC6C598-Q1 characterization is for for operation over the operating ambient temperature range of −40°C to 125°C.

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Technical documentation

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Type Title Date
* Data sheet TLC6C598-Q1 Power Logic 8-Bit Shift Register LED Driver datasheet (Rev. D) PDF | HTML 13 Sep 2016
Application note TLC6C598-Q1, TLC6C5912-Q1 Shift Register LED Driver Application 04 Jun 2015
User guide TLC6C598-Q1 and TLC6C5912-Q1 Reference Design 29 Nov 2012

Design & development

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Simulation model

TLC6C598 IBIS Model

SLIM316.ZIP (46 KB) - IBIS Model
Simulation model

TLC6C598 Unencrypted PSpice Transient Model Package (Rev. B)

SLIM311B.ZIP (29 KB) - PSpice Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs

TIDA-010076 — Daisy-chained power and data over single pair Ethernet (T1) reference design

The TIDA-010076 shows the transfer of 220-W power and 100-Mbit/s data over SPE. Communication systems in daisy-chain topology need significantly less hardware and wiring than conventional systems in star-topology. When combined with single-pair Ethernet (SPE, 100BASE-T1) and power over data line, (...)
Design guide: PDF
Schematic: PDF
Package Pins Download
SOIC (D) 16 View options
TSSOP (PW) 16 View options

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