TLK3132

LAST TIME BUY

2-channel 600-Mbps to 3.75-Gbps multi-rate transceiver

Product details

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
PBGA (ZEN) 196 225 mm² 15 x 15
  • Two Channel 600Mbps to 3.75Gbps Multi-Rate Transceiver
  • Supports 1X/2X Fibre Channel (FC), CPRI (x1/x2/x4), OBSAI (x1/x2/x4), and 1GbE (1000Base-X) Data Rates
  • IEEE Compliant 1000Base-X PCS Support
  • Supports Independent Channel SERDES Operation Modes in 8/10 Bit Data Modes (TBI and 8 Bit + Control)
  • Serial Side Transmit De-Emphasis and Receive Adaptive Equalization to Allow Extended Backplane Reach
  • Low Jitter LC Oscillator Jitter-Cleaner Allows use of Poor Quality REFCLK
  • Full Datapath Loopback Capability (Serial/Parallel Side)
  • Supports PRBS 27-1 and 223 – 1 Gen/Verify. Supports Standard Defined CRPAT, High and Low Frequency, and Mixed Frequency Testing.
  • GMII/RGMII: HSTL Class 1 I/O With On-Chip Termination: Programmable Input and 50 Output (1.5 and 1.8V Power Supply)
  • GMII/RGMII: Source and Data Centered I/O Timing Modes
  • Supports Jumbo Packet (9600 Byte Maximum) Operation
  • MDIO: IEEE 802.3 Clause 22 Compliant Management Data Input / Output Interface Modes (Either 1.2V or 2.5V MDIO I/O)
  • 1.2V Core, 1.5V/1.8V HSTL I/O Supply, and 2.5V LVCMOS I/O Supply
  • JTAG: IEEE 1149.1/1149.6 Test Interface
  • ±200 ppm Clock Tolerance in 1000Base-X Receive Datapaths
  • 90 nm Advanced CMOS Technology
  • Package: PBGA, 15×15mm, 196 Ball, 1mm Pitch
  • 1.1W Maximum Power Dissipation at 2CH 3.75 Gbps (1.5V HSTL Mode, Input HSTL Termination Disabled)
  • Asymmetric RX/TX Rates Supported
  • Industrial Ambient Operating Temperature (–40°C to 85°C) at Full Rate
  • Two Channel 600Mbps to 3.75Gbps Multi-Rate Transceiver
  • Supports 1X/2X Fibre Channel (FC), CPRI (x1/x2/x4), OBSAI (x1/x2/x4), and 1GbE (1000Base-X) Data Rates
  • IEEE Compliant 1000Base-X PCS Support
  • Supports Independent Channel SERDES Operation Modes in 8/10 Bit Data Modes (TBI and 8 Bit + Control)
  • Serial Side Transmit De-Emphasis and Receive Adaptive Equalization to Allow Extended Backplane Reach
  • Low Jitter LC Oscillator Jitter-Cleaner Allows use of Poor Quality REFCLK
  • Full Datapath Loopback Capability (Serial/Parallel Side)
  • Supports PRBS 27-1 and 223 – 1 Gen/Verify. Supports Standard Defined CRPAT, High and Low Frequency, and Mixed Frequency Testing.
  • GMII/RGMII: HSTL Class 1 I/O With On-Chip Termination: Programmable Input and 50 Output (1.5 and 1.8V Power Supply)
  • GMII/RGMII: Source and Data Centered I/O Timing Modes
  • Supports Jumbo Packet (9600 Byte Maximum) Operation
  • MDIO: IEEE 802.3 Clause 22 Compliant Management Data Input / Output Interface Modes (Either 1.2V or 2.5V MDIO I/O)
  • 1.2V Core, 1.5V/1.8V HSTL I/O Supply, and 2.5V LVCMOS I/O Supply
  • JTAG: IEEE 1149.1/1149.6 Test Interface
  • ±200 ppm Clock Tolerance in 1000Base-X Receive Datapaths
  • 90 nm Advanced CMOS Technology
  • Package: PBGA, 15×15mm, 196 Ball, 1mm Pitch
  • 1.1W Maximum Power Dissipation at 2CH 3.75 Gbps (1.5V HSTL Mode, Input HSTL Termination Disabled)
  • Asymmetric RX/TX Rates Supported
  • Industrial Ambient Operating Temperature (–40°C to 85°C) at Full Rate

The TLK3132 is a flexible two channel independently configurable serial transceiver. It can be configured to be compliant with the 1000Base-X 1Gbps Ethernet Specification (Auto-Negotiation not supported). The TLK3132 provides high-speed bi-directional point-to-point data transmissions with up to 15 Gbps of raw data transmission capacity. The primary application of this device is in backplanes and front panel connections requiring 3.75Gbps connections over controlled impedance media of approximately 50. The transmission media can be printed circuit board (PCB) traces, copper cables or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling into the lines.

The TLK3132 performs the parallel-to-serial, serial-to-parallel conversion, and clock extraction functions for a physical layer interface. The TLK3132 also provides 1000Base-X (PCS) layer functionality described in Clause 36 of 802.3-2002. The serial transmitter is implemented using differential Current Mode Logic (CML) with integrated termination resistors.

Many common applications may be enabled by way of externally available control pins. Detailed control of the TLK3132 on a per channel basis is available by way of accessing a register space of control bits available through a two-wire access port called the Management Data Input/Output (MDIO) interface.

The PCS (Physical Coding Sublayer) functions such as the CTC FIFO are designed to be compliant for a 1000Base-X PCS link. However, each of the PCS functions may be disabled or bypassed until the TLK3132 is operating at its most basic state, that of a simple two channel 10-bit SERDES suitable for a wide range of applications such as CPRI or OBSAI wireless infrastructure links.

The differential output swing for the TLK3132 is suitable for compliance with IEEE 802.3 Gigabit Ethernet links, which is also suitable for CPRI LV serial links. The TLK3132 provides for setting larger output signal swing suitable for CPRI HV links by setting an appropriate register bit available though MDIO.

The TLK3132 is a flexible two channel independently configurable serial transceiver. It can be configured to be compliant with the 1000Base-X 1Gbps Ethernet Specification (Auto-Negotiation not supported). The TLK3132 provides high-speed bi-directional point-to-point data transmissions with up to 15 Gbps of raw data transmission capacity. The primary application of this device is in backplanes and front panel connections requiring 3.75Gbps connections over controlled impedance media of approximately 50. The transmission media can be printed circuit board (PCB) traces, copper cables or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling into the lines.

The TLK3132 performs the parallel-to-serial, serial-to-parallel conversion, and clock extraction functions for a physical layer interface. The TLK3132 also provides 1000Base-X (PCS) layer functionality described in Clause 36 of 802.3-2002. The serial transmitter is implemented using differential Current Mode Logic (CML) with integrated termination resistors.

Many common applications may be enabled by way of externally available control pins. Detailed control of the TLK3132 on a per channel basis is available by way of accessing a register space of control bits available through a two-wire access port called the Management Data Input/Output (MDIO) interface.

The PCS (Physical Coding Sublayer) functions such as the CTC FIFO are designed to be compliant for a 1000Base-X PCS link. However, each of the PCS functions may be disabled or bypassed until the TLK3132 is operating at its most basic state, that of a simple two channel 10-bit SERDES suitable for a wide range of applications such as CPRI or OBSAI wireless infrastructure links.

The differential output swing for the TLK3132 is suitable for compliance with IEEE 802.3 Gigabit Ethernet links, which is also suitable for CPRI LV serial links. The TLK3132 provides for setting larger output signal swing suitable for CPRI HV links by setting an appropriate register bit available though MDIO.

Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 5
Type Title Date
* Data sheet 2-Channel Multi-Rate Transceiver datasheet (Rev. A) 17 Dec 2009
User guide User's Guide for Sonic MDIO Software 26 Nov 2013
EVM User's guide TLK3132 2-Channel Multi-Rate Transceiver EVM User's Guide 20 Nov 2013
White paper Implementing a CameraLink HS Interface Using the TLK3134 30 Mar 2012
Application note TLK313x/CDCM7005 Multi-hop Performance 01 Nov 2009

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

TLK3132 IBIS Model Version 1.2

SLLM054.ZIP (307 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
Package Pins Download
PBGA (ZEN) 196 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos