SLAS509F December 2006  – December 2014 TLV320AIC3106

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Simplified Diagram
  5. Revision History
  6. Description (continued)
  7. Device Comparison Table
  8. Pin Configuration and Functions
  9. Specifications
    1. 9.1Absolute Maximum Ratings
    2. 9.2ESD Ratings
    3. 9.3Recommended Operating Conditions
    4. 9.4Thermal Information
    5. 9.5Electrical Characteristics
    6. 9.6Timing Requirements: Audio Data Serial Interface
    7. 9.7Typical Characteristics
  10. 10Parameter Measurement Information
  11. 11Detailed Description
    1. 11.1Overview
    2. 11.2Functional Block Diagram
    3. 11.3Feature Description
      1. 11.3.1 Hardware Reset
      2. 11.3.2 Digital Audio Data Serial Interface
        1. 11.3.2.1Right-Justified Mode
        2. 11.3.2.2Left-Justified Mode
        3. 11.3.2.3I2S Mode
        4. 11.3.2.4DSP Mode
        5. 11.3.2.5TDM Data Transfer
      3. 11.3.3 Audio Data Converters
        1. 11.3.3.1Audio Clock Generation
        2. 11.3.3.2Stereo Audio ADC
          1. 11.3.3.2.1Stereo Audio ADC High-Pass Filter
          2. 11.3.3.2.2Automatic Gain Control (AGC)
            1. 11.3.3.2.2.1Target Level
            2. 11.3.3.2.2.2Attack Time
            3. 11.3.3.2.2.3Decay Time
            4. 11.3.3.2.2.4Noise Gate Threshold
            5. 11.3.3.2.2.5Maximum PGA Gain Applicable
        3. 11.3.3.3Stereo Audio DAC
          1. 11.3.3.3.1Digital Audio Processing for Playback
          2. 11.3.3.3.2Digital Interpolation Filter
          3. 11.3.3.3.3Delta-Sigma Audio DAC
          4. 11.3.3.3.4Audio DAC Digital Volume Control
          5. 11.3.3.3.5Increasing DAC Dynamic Range
          6. 11.3.3.3.6Analog Output Common-Mode Adjustment
          7. 11.3.3.3.7Audio DAC Power Control
      4. 11.3.4 Audio Analog Inputs
      5. 11.3.5 Analog Fully Differential Line Output Drivers
      6. 11.3.6 Analog High Power Output Drivers
      7. 11.3.7 Input Impedance and VCM Control
      8. 11.3.8 General-Purpose I/O
      9. 11.3.9 Digital Microphone Connectivity
      10. 11.3.10Micbias Generation
      11. 11.3.11Short Circuit Output Protection
      12. 11.3.12Jack/Headset Detection
    4. 11.4Device Functional Modes
      1. 11.4.1Bypass Path Mode
        1. 11.4.1.1Analog Input Bypass Path Functionality
        2. 11.4.1.2ADC PGA Signal Bypass Path Functionality
        3. 11.4.1.3Passive Analog Bypass During Powerdown
      2. 11.4.2Digital Audio Processing for Record Path
    5. 11.5Programming
      1. 11.5.1Digital Control Serial Interface
        1. 11.5.1.1SPI Control Mode
          1. 11.5.1.1.1SPI Communication Protocol
          2. 11.5.1.1.2Limitation on Register Writing
          3. 11.5.1.1.3Continuous Read / Write Operation
        2. 11.5.1.2I2C Control Interface
          1. 11.5.1.2.1I2C BUS Debug in a Glitched System
    6. 11.6Register Maps
    7. 11.7Output Stage Volume Controls
  12. 12Application and Implementation
    1. 12.1Application Information
    2. 12.2Typical Application
      1. 12.2.1Design Requirements
      2. 12.2.2Detailed Design Procedure
      3. 12.2.3Application Curves
  13. 13Power Supply Recommendations
  14. 14Layout
    1. 14.1Layout Guidelines
    2. 14.2Layout Example
  15. 15Device and Documentation Support
    1. 15.1Trademarks
    2. 15.2Electrostatic Discharge Caution
    3. 15.3Glossary
  16. 16Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGZ|48
  • ZQE|80
Orderable Information

1 Features

  • Stereo Audio DAC
    • 102-dBA Signal-to-Noise Ratio
    • 16/20/24/32-Bit Data
    • Supports Rates From 8 kHz to 96 kHz
    • 3D/Bass/Treble/EQ/De-Emphasis Effects
    • Flexible Power Saving Modes and Performance are Available
  • Stereo Audio ADC
    • 92-dBA Signal-to-Noise Ratio
    • Supports Rates From 8 kHz to 96 kHz
    • Digital Signal Processing and Noise Filtering Available During Record
  • Ten Audio Input Pins
    • Programmable in Single-Ended or Fully Differential Configurations
    • 3-State Capability for Floating Input Configurations
  • Seven Audio Output Drivers
    • Stereo Fully Differential or Single-Ended Headphone Drivers
    • Fully Differential Stereo Line Outputs
    • Fully Differential Mono Output
  • Low Power: 15-mW Stereo 48-kHz Playback With 3.3-V Analog Supply
  • Ultralow-Power Mode with Passive Analog Bypass
  • Programmable Input/Output Analog Gains
  • Automatic Gain Control (AGC) for Record
  • Programmable Microphone Bias Level
  • Programmable PLL for Flexible Clock Generation
  • Control Bus Selectable SPI or I2C
  • Audio Serial Data Bus Supports I2S, Left/Right-Justified, DSP, and TDM Modes
  • Alternate Serial PCM/I2S Data Bus for Easy Connection to Bluetooth™ Module
  • Concurrent Digital Microphone and Analog Microphone Support Available
  • Extensive Modular Power Control
  • Power Supplies:
    • Analog: 2.7 V–3.6 V.
    • Digital Core: 1.65 V–1.95 V
    • Digital I/O: 1.1 V–3.6 V
    Packages: 5.00 mm × 5.00 mm 80-pin VFBGA;
    7.00 mm × 7.00 mm 48-pin QFN

2 Applications

  • Digital Cameras
  • Smart Cellular Phones

3 Description

The TLV320AIC3106 is a low-power stereo audio codec with stereo headphone amplifier, as well as multiple inputs and outputs programmable in single-ended or fully differential configurations. Extensive register-based power control is included, enabling stereo 48-kHz DAC playback as low as 15 mW from a 3.3-V analog supply, making it ideal for portable battery-powered audio and telephony applications.

The record path of the TLV320AIC3106 contains integrated microphone bias, digitally controlled stereo microphone preamplifier, and automatic gain control (AGC), with mix/mux capability among the multiple analog inputs. Programmable filters are available during record which can remove audible noise that can occur during optical zooming in digital cameras.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
TLV320AIC3106BGA MICROSTAR JUNIOR (80)5.00 mm x 5.00 mm
VQFN (48)7.00 mm x 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

4 Simplified Diagram

TLV320AIC3106 SimplifiedDiagram_slas509.png