7.3.1 Hardware Reset

The TLV320AIC3109-Q1 requires a hardware reset after power-up for proper operation. After all power supplies are at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not performed, the TLV320AIC3109-Q1 may not respond properly to register reads or writes.

This device also offers a software reset (page 0, register 1) that can be used by the host to reset all registers on page 0 and page 1 to their reset values. In cases where changes are needed only for routing or volume-control registers, these changes can be accomplished by writing directly to the appropriate registers rather than using the software or hardware reset.

In cases where the ESD events generate a device reset, a minimum 1-nF capacitor is recommended to be connected between the RESET pin and DVSS. This capacitor avoids ESD events that can place the codec in default state.

7.3.2 Digital Audio Data Serial Interface

Audio data are transferred between the host processor and the TLV320AIC3109-Q1 via the digital audio data serial interface. The audio bus of the TLV320AIC3109-Q1 can be configured for left- or right-justified, I²S, DSP, or TDM modes of operation, where communication with standard PCM interfaces is supported within TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word clock (WCLK) and bit clock (BCLK) can be independently configured in either master or slave mode for flexible connectivity to a wide variety of processors.

The word clock (WCLK) is used to define the beginning of a frame, and can be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the selected ADC and DAC sampling frequency.

The bit clock (BCLK) is used to clock in and out the digital audio data across the serial bus. When in master mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock mode. In continuous transfer mode, only the minimal number of bit clocks required to transfer the audio data are generated, so in general the number of bit clocks per frame is two times the data width. For example, if the data width is chosen as 16 bits, then 32-bit clocks are generated per frame. If the bit clock signal in master mode is to be used by a PLL in another device, then the 16-bit or 32-bit data-width selections are recommended be used. These cases result in a low-jitter bit clock signal being generated, with frequencies of 32 f_S or 64 f_S. For a 20-bit and 24-bit data width in master mode, the bit clocks generated in each frame are not all of equal period because the device does not have a clean 40-f_S or 48-f_S clock signal readily available. The average frequency of the bit clock signal is still accurate in these cases (40 f_S or 48 f_S), but the resulting clock signal has higher jitter than in the 16-bit and 32-bit cases.

In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen. The TLV320AIC3109-Q1 further includes programmability to place the DOUT line in the high-impedance state during all bit clocks when valid data are not being sent. By combining this capability with the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, resulting in multiple codecs able to use a single audio serial data bus.

When the digital audio data serial interface is powered down when configured in master mode, the pins associated with the interface are put into a high-impedance state.

The following subsections describe the supported data interface protocols. These protocols can be used for left- and right-channel applications. Only one of the two possible channels can be selected because the TLV320AIC3109-Q1 is a mono audio codec. Only the left channel is valid for DOUT (output data). For DIN (input data), valid data can be selected with bits 4 and 3 of register 7, page 0.

7.3.2.1 Right-Justified Mode

In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of the word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock. Figure 12 shows a timing diagram of this operation.

Figure 12. Right-Justified Serial Data Bus Mode Operation

7.3.2.2 Left-Justified Mode

In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling edge of the word clock. Similarly, the MSB of the left channel is valid on the rising edge of the bit clock following the rising edge of the word clock. Figure 13 shows a timing diagram of this operation.

Figure 13. Left-Justified Serial Data Bus Mode Operation

7.3.2.3 I²S Mode

In I²S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock. Figure 14 shows a timing diagram of this operation.

Figure 14. I²S Serial Data Bus Mode Operation

7.3.2.4 DSP Mode

In DSP mode, the rising edge of the word clock starts the data transfer with the left-channel data first, immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock. Figure 15 shows a timing diagram of this operation.

Figure 15. DSP Serial Data Bus Mode Operation

7.3.2.5 TDM Data Transfer

Time-division multiplexed data transfer can be realized in any of the left-justified transfer modes if the 256-clock bit-clock mode is selected, although it is recommended to be used in either left-justified mode or DSP mode. By changing the programmable offset, the bit clock in each frame where the data begins can be changed, and the serial data output driver (DOUT) can also be programmed to the high-impedance state during all bit clocks except when valid data is being put onto the bus. This format allows other codecs to be programmed with different offsets and to drive their data onto the same DOUT line, just in a different slot. For incoming data, the codec simply ignores data on the bus except when expected based on the programmed offset.

The location of the data when an offset is programmed is different depending on what transfer mode is selected. In DSP mode, both the left and right channels of data are transferred immediately adjacent to each other in the frame. This configuration differs from left-justified mode, where the left- and right-channel data are always a half-frame apart in each frame. In this case, when the offset is programmed from zero to some higher value, both the left- and right-channel data move across the frame, but still stay a full half-frame apart from each other. Figure 16 shows the TDM transfer for DSP mode and left-justified mode.

Figure 16. DSP Mode and Left-Justified Mode, Showing the
Effect of a Programmed Data-Word Offset

7.3.3 Audio Data Converters

The TLV320AIC3109-Q1 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters also can operate at different sampling rates in various combinations, as described in this section.

The data converters are based on the concept of an f_S(ref) rate that is used internal to the device, and is related to the actual sampling rates of the converters through a series of ratios. For typical sampling rates, f_S(ref) is either 44.1 kHz or 48 kHz, although f_S(ref) can realistically be set over a wider range of rates up to 53 kHz, with additional restrictions if the PLL is used. This concept is used to set the sampling rates of the ADC and DAC, and also to enable high-quality playback of low-sampling-rate data without high-frequency audible noise being generated.

The sampling rate of the ADC and DAC is determined by the clock divider (NCODEC). The sampling rate can be set to f_S(ref) / NCODEC or 2 × f_S(ref) / NCODEC, with NCODEC being 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6 for both the NDAC and NADC settings. In the TLV320AIC3109-Q1, NDAC and NADC must be set to the same value because the device only supports a common sampling rate for the ADC and DAC channels. Therefore, NCODEC = NDAC = NADC and this value is programmed by setting the value of bits 7–4 equal to the value of bits 3–0 in register 2, page 0.

7.3.3.1 Audio Clock Generation

The audio converters in the TLV320AIC3109-Q1 need an internal audio master clock at a frequency of 256 f_S(ref), which can be obtained in a variety of manners from an external clock signal applied to the device. Figure 17 shows a detailed diagram of the audio clock section of the TLV320AIC3109-Q1.

Figure 17. Audio Clock Generation Processing

The device can accept an MCLK input from 512 kHz to 50 MHz that can then be passed through either a programmable divider or a PLL to get the proper internal audio master clock required by the device. The BCLK input can also be used to generate the internal audio master clock.

A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequencies available in the system. This device includes a highly programmable PLL to accommodate such situations easily. The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with particular focus paid to the standard MCLK rates already widely used.

When the PLL is disabled,

Equation 1. f_S(ref) = CLKDIV_IN / (128 × Q)

where

• Q = 2, 3…17; Q is register-programmable and can be set by bits 6–3 in register 3, page 0

CLKDIV_IN can be MCLK or BCLK, selected by register 102, bits 7–6.

NOTE

When NCODEC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In this mode, MCLK can be as high as 50 MHz, and f_S(ref) must fall within 39 kHz to 53 kHz, inclusively.

When the PLL is enabled,

Equation 2. f_S(ref) = (PLLCLK_IN × K × R) / (2048 × P)

where

• P = 1, 2, 3…8
• R = 1, 2…16
• K = J.D
• J = 1, 2, 3…63
• D = 0000, 0001, 0002, 0003…9998, 9999
• PLLCLK_IN can be MCLK or BCLK, selected by bits 5–4 in register 102, page 0

P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal point), whereas D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision). P can be set by bits 2–0 in register 3, page 0. R can be set by bits 3–0 in register 11, page 0. J can be set by bits 7–2 in register 4, page 0. The most-significant bits of D can be set by bits 7–0 in register 5, page 0, and the least-significant bits of D can be set by bits 7–2 in register 6, page 0.

Examples:

If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified performance:

2 MHz ≤ (PLLCLK_IN / P) ≤ 20 MHz
80 MHz ≤ (PLLCLK _IN × K × R / P) ≤ 110 MHz
4 ≤ J ≤ 55

When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied to meet specified performance:

10 MHz ≤ PLLCLK _IN / P ≤ 20 MHz
80 MHz ≤ PLLCLK _IN × K × R / P ≤ 110 MHz
4 ≤ J ≤ 11
R = 1

Example:

MCLK = 12 MHz and f_S(ref) = 44.1 kHz
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example:

MCLK = 12 MHz and f_S(ref) = 48 kHz
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

Table 1 lists several example cases of typical MCLK rates and how to program the PLL to achieve f_S(ref) = 44.1 kHz or 48 kHz.

Table 1. Typical MCLK Rates

MCLK (MHz)	P	R	J	D	ACHIEVED fS(ref)	% ERROR
fS(ref) = 44.1 kHz
2.8224	1	1	32	0	44,100	0
5.6448	1	1	16	0	44,100	0
12	1	1	7	5264	44,100	0
13	1	1	6	9474	44,099.71	–0.0007
16	1	1	5	6448	44,100	0
19.2	1	1	4	7040	44,100	0
19.68	1	1	4	5893	44,100.3	0.0007
48	4	1	7	5264	44,100	0
fS(ref) = 48 kHz
2.048	1	1	48	0	48,000	0
3.072	1	1	32	0	48,000	0
4.096	1	1	24	0	48,000	0
6.144	1	1	16	0	48,000	0
8.192	1	1	12	0	48,000	0
12	1	1	8	1920	48,000	0
13	1	1	7	5618	47,999.71	–0.0006
16	1	1	6	1440	48,000	0
19.2	1	1	5	1200	48,000	0
19.68	1	1	4	9951	47,999.79	–0.0004
48	4	1	8	1920	48,000	0

7.3.3.2 Mono Audio ADC

The TLV320AIC3109-Q1 includes a mono audio ADC that uses a delta-sigma modulator with 128-times oversampling in single-rate mode, followed by a digital decimation filter. The ADC supports sampling rates from 8 kHz to 96 kHz. Whenever the ADC or DAC is in operation, the device requires that an audio master clock be provided and appropriate audio clock generation be set up within the device.

The integrated digital decimation filter removes high-frequency content and downsamples the audio data from an initial sampling rate of 128 f_S to the final output sampling rate of f_S. The decimation filter provides a linear phase output response with a group delay of 17 / f_S. The –3-dB bandwidth of the decimation filter extends to 0.45 f_S and scales with the sample rate (f_S). The filter has minimum 75-dB attenuation over the stop band from 0.55 f_S to 64 f_S. The device also provide options to select the corner frequency of the digital high-pass filter.

Requirements for analog antialiasing filtering are very relaxed because of the oversampling nature of the audio ADC and the integrated digital decimation filtering. The TLV320AIC3109-Q1 integrates a second-order analog antialiasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimation filter, provides sufficient antialiasing filtering without requiring additional external components.

The ADC is preceded by a programmable gain amplifier (PGA) that allows analog gain control from 0 dB to 59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping algorithm that only changes the actual volume level by one 0.5-dB step every one or two ADC output samples, depending on the register programming (see registers 19 and 22, page 0). This soft-stepping ensures that volume control changes occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and on power-down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled by programming a register bit. When soft-stepping is enabled, the audio master clock must be applied to the device after the ADC power-down register is written to ensure the soft-stepping to mute has completed. When the ADC power-down flag is no longer set, the audio master clock can be shut down.

An additional auxiliary PGA is provided to allow the mixing of the DAC output signals with an input not routed through the ADC. This PGA has the same specifications as the ADC PGA.

7.3.3.2.1 Mono Audio ADC High-Pass Filter

Often in audio applications, the dc offset needs to be removed from the converted audio data stream. The TLV320AIC3109-Q1 has a programmable first-order, high-pass filter that can be used for this purpose. The digital filter coefficients are in 16-bit format and therefore use two 8-bit registers for each of the three coefficients, N0, N1, and D1. Equation 3 shows the form of the digital high-pass filter transfer function:

Equation 3.

Programming the channel is done by writing to registers 65–70, page 1. After the coefficients are loaded, these ADC high-pass filter coefficients can be selected by writing to bit 7 in register 107, page 0, and the high-pass filter can be enabled by writing to bit 7 in register 12, page 0.

7.3.3.2.2 Automatic Gain Control (AGC)

An automatic gain control (AGC) circuit is included with the ADC and can be used to maintain nominally constant output signal amplitude when recording speech signals (the AGC can be fully disabled if not needed). This circuitry automatically adjusts the PGA gain when the input signal becomes overly loud or very weak, such as when a person speaking into a microphone moves closer or farther from the microphone. The AGC algorithm has several programmable settings, including target level, attack and decay time constants, noise threshold, and maximum PGA gain applicable that allow the algorithm to be fine-tuned for any particular application. These AGC features are explained in this section, and Figure 18 illustrates their operation. The algorithm uses the absolute average of the signal (which is the average of the absolute value of the signal) as a measure of the nominal amplitude of the output signal.

Figure 18. Typical Operation of the AGC Algorithm During Speech Recording

7.3.3.2.2.1 Target Level

Target value represents the nominal output level at which the AGC attempts to hold the ADC output signal level. The TLV320AIC3109-Q1 allows programming of eight different target levels, which can be programmed from –5.5 dB to –24 dB relative to a full-scale signal. The target level is recommended to be set with enough margin to avoid clipping at the occurrence of loud sounds because the device reacts to the signal absolute average and not to peak levels.

7.3.3.2.2.2 Attack Time

Attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud. It Attack time can be varied from 7 ms to 1,408 ms. The attack time can be programmed by writing to register 105, page 0.

7.3.3.2.2.3 Decay Time

Decay time determines how quickly the PGA gain is increased when the input signal is too low. It Decay time can be varied in the range from 0.05 s to 22.4 s. Decay time is programmed by writing to register 106, page 0.

The actual maximum AGC decay time is based on a counter length, so the maximum decay time scales with the clock setup that is used. Table 2 lists the relationship of the NCODEC ratio to the maximum time available for the AGC decay. In practice, these maximum times are extremely long for audio applications and must not limit any practical AGC decay time that is needed by the system.

Table 2. AGC Decay Time Restriction

NCODEC RATIO	MAXIMUM DECAY TIME (SECONDS)
1	4
1.5	5.6
2	8
2.5	9.6
3	11.2
3.5	11.2
4	16
4.5	16
5	19.2
5.5	22.4
6	22.4

7.3.3.2.2.4 Noise Gate Threshold

If the input speech average value falls below the level determined by this threshold, the AGC considers the speech input to be silent and brings down the gain to 0 dB in steps of 0.5 dB every sample period and sets the noise threshold flag. The gain stays at 0 dB unless the input speech signal average rises above the noise threshold setting. This threshold ensures that noise is not gained up during times of silence. The noise threshold level in the AGC algorithm is programmable from –30 dB to –90 dB relative to full-scale. A disable noise gate feature is also available. This operation includes programmable debounce and hysteresis functionality to avoid the AGC gain from cycling between high gain and 0 dB when signals are near the noise threshold level. When the noise threshold flag is set, ignore the status of gain applied by the AGC and the saturation flag.

7.3.3.2.2.5 Maximum PGA Gain Applicable

The maximum PGA gain that can be applied by the AGC algorithm can be restricted. This restriction can be used for limiting PGA gain in situations where environmental noise is greater than the programmed noise threshold. The PGA gain can be programmed from 0 dB to 59.5 dB in steps of 0.5 dB.

The time constants are correct when the ADC is not in double-rate audio mode. The time constants are achieved by using the f_S(ref) value programmed in the control registers. However, if the f_S(ref) is set in the registers (for example, to 48 kHz), but the actual audio clock or PLL programming results in a different f_S(ref) in practice, then the time constants are incorrect; see the Decay Time section for more information.

7.3.4 Mono Audio DAC

The TLV320AIC3109-Q1 includes a mono audio DAC supporting sampling rates from 8 kHz to 96 kHz. The DAC consists of a digital audio processing block, a digital interpolation filter, a multi-bit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced performance at low sampling rates through increased oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed within the audio band to beyond 20 kHz. This is realized by keeping the upsampled rate constant at 128 f_S(ref) and changing the oversampling ratio when the input sample rate changes. For an f_S(ref) of 48 kHz, the digital delta-sigma modulator always operates at a rate of 6.144 MHz, which ensures that quantization noise generated within the delta-sigma modulator stays low within the frequency band below 20 kHz at all sample rates. Similarly, for an f_S(ref) rate of 44.1 kHz, the digital delta-sigma modulator always operates at a rate of 5.6448 MHz.

The following restrictions apply in the case when the PLL is powered down and double-rate audio mode is enabled in the DAC.

• Allowed Q values = 4, 8, 9, 12, 16
• Q values where equivalent f_S(ref) can be achieved by turning on the PLL
• Q = 5, 6, 7 (set P = 5, 6, or 7, K = 16, and PLL enabled)
• Q = 10, 14 (set P = 5 or 7, K = 8, and PLL enabled)

7.3.4.1 Digital Audio Processing for Playback

The DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment, and speaker equalization. The de-emphasis function is implemented by a programmable digital filter block with fully programmable coefficients (see registers 21–26, page 1). If de-emphasis is not required in a particular application, this programmable filter block can be used for some other purpose. Equation 4 gives the de-emphasis filter transfer function:

Equation 4.

where

• The N0, N1, and D1 coefficients are fully programmable individually

Table 3 lists the coefficients that must be loaded to implement standard de-emphasis filters.

Table 3. De-Emphasis Coefficients for Common Audio Sampling Rates

SAMPLING FREQUENCY	N0	N1	D1
32 kHz	16,950	–1,220	17,037
44.1 kHz	15,091	–2,877	20,555
48 kHz(1)	14,677	–3,283	21,374

(1) The 48-kHz coefficients listed in Table 3 are used as defaults.

In addition to the de-emphasis filter block, the DAC digital effects processing includes a fourth-order digital IIR filter with programmable coefficients. This filter is implemented as a cascade of two biquad sections with the frequency response given by:

Equation 5.

The N and D coefficients are fully programmable and the entire filter can be enabled or bypassed. The structure of the filtering when configured for channel processing is illustrated in Figure 19, with LB1 corresponding to the first biquad filter using coefficients N0, N1, N2, D1, and D2. LB2 similarly corresponds to the second biquad filter using coefficients N3, N4, N5, D4, and D5.

Figure 19. Structure of Digital Effects Processing for Channel Processing

The coefficients for this filter implement a variety of sound effects, with bass boost or treble boost being the most commonly used in portable audio applications. The default N and D coefficients in the device are given in Table 4 and implement a shelving filter with 0-dB gain from dc to approximately 150 Hz, at which point the filter rolls off to a 3-dB attenuation for higher frequency signals, thus giving a 3-dB boost to signals below 150 Hz. The N and D coefficients are represented by 16-bit, 2's-complement numbers with values ranging from –32,768 to 32,767.

Table 4. Default Digital Effects Processing Filter Coefficients,
When in Independent Channel Processing Configuration

COEFFICIENTS
N0 = N3	D1 = D4	N1 = N4	D2 = D5	N2 = N5
27,619	32,131	–27,034	–31,506	26,461

The digital effects filters are recommended to be disabled when the filter coefficients are being modified. When new coefficients are being written to the device over the control port, a filter using partially updated coefficients can possibly implement an unstable system and lead to oscillation or objectionable audio output. By disabling the filters, changing the coefficients, and then reenabling the filters, these types of effects can be entirely avoided.

7.3.5 Audio Analog Inputs

The TLV320AIC3109-Q1 includes two single-ended audio inputs. These pins connect through series resistors and switches to the virtual ground pins of two fully differential operational amplifiers. By selecting to turn on only one set of switches per operational amplifier at a time, the inputs can be multiplexed effectively to the PGA.

By selecting to turn on multiple sets of switches per operational amplifier at a time, mixing can also be achieved. Mixing of multiple inputs can easily lead to PGA outputs that exceed the range of the internal operational amplifiers, resulting in saturation and clipping of the mixed output signal. Whenever mixing is being implemented, take adequate precautions to avoid such saturation from occurring. In general, the mixed signal should not exceed 2 V_PP (single-ended).

In most mixing applications, there is also a general need to adjust the levels of the individual signals being mixed. For example, if a soft signal and a large signal are to be mixed and played together, the soft signal generally should be amplified to a level comparable to the large signal before mixing. In order to accommodate this need, the TLV320AIC3109-Q1 includes input level controls on each of the individual inputs before being mixed or multiplexed into the ADC PGA, with gain programmable from 0 dB to –12 dB in 1.5-dB steps. This input level control is not intended to be a volume control, but instead used occasionally for level setting. Soft-stepping of the input level control settings is implemented in this device, with the speed and functionality following the settings used by the ADC PGA for soft-stepping.

Figure 20 shows the single-ended mixing configuration for the PGA, which enables mixing of the signals LINE1L and LINE1R. The PGA MIX is similar, enabling mixing of the LINE1R and LINE1L signals.

Figure 20. Single-Ended Analog Input Mixing Configuration

7.3.6 Analog Fully Differential Line Output Drivers

The TLV320AIC3109-Q1 has two fully differential line output drivers, each capable of driving a 10-kΩ differential load. Figure 21 and Figure 22 illustrate the output stage design leading to the fully differential line output drivers. This design includes extensive capability to adjust signal levels independently before any mixing occurs, beyond that already provided by the PGA gain and the DAC digital volume control.

The PGA signal refers to the output of the ADC PGA stage that is passed around the ADC to the output stage. PGA_AUX is the output of the auxiliary PGA. The DAC output can be sent to the output driver and mixed with the PGA or PGA_AUX signal. Undesired signals can also be disconnected from the MIX through register control.

Figure 21. Architecture of the Output Stage Leading to the Fully Differential Line Output Drivers

Figure 22. Detail of the Volume Control and Mixing Function in Figure 19 and Figure 29

The DAC signal is the output of the mono audio DAC that can be steered by register control based on the requirements of the system. If mixing of the DAC audio with other signals is not required, and the DAC output is only needed at the mono line outputs, then use the routing through the DAC_3 path to the fully differential line outputs. This configuration results in lower-power operation because the analog volume controls and mixing blocks ahead of these drivers can be powered down.

If instead the DAC analog output must be routed to multiple output drivers simultaneously (such as to LEFT_LOP, LEFT_LOM and RIGHT_LOP, RIGHT_LOM) or must be mixed with other analog signals, then switch the DAC outputs through the DAC_1 path. This option provides the maximum flexibility for routing of the DAC analog signals to the output drivers.

The TLV320AIC3109-Q1 includes an output level control on each output driver with limited gain adjustment from 0 dB to 9 dB. The output driver circuitry in this device is designed to provide a low-distortion output when playing full-scale mono DAC signals at a 0-dB gain setting. However, a higher amplitude output can be obtained at the cost of increased signal distortion at the output. This output level control allows this tradeoff to be made based on the requirements of the end equipment. This output level control is not intended to be used as a standard output volume control, but is expected to be used only sparingly for level setting (that is, for adjustment of the full-scale output range of the device).

Each differential line output driver can be powered down independently of the others when not needed in the system. When placed into powerdown through register programming, the driver output pins are placed into a high-impedance state.

7.3.7 Analog High-Power Output Drivers

The TLV320AIC3109-Q1 includes two high-power output drivers with extensive flexibility in their usage. These output drivers are individually capable of driving 30 mW each into a 16-Ω load in single-ended configuration, and can be used in pairs connected in a bridge-terminated load (BTL) configuration between two driver outputs.

The high-power output drivers can be configured in a variety of ways, including:

1. Driving up to two single-ended output signals
2. Driving one single-ended output signal, with the remaining driver driving a fixed VCM level

The output stage architecture leading to the high-power output drivers is provided in Figure 23, with the volume control and mixing blocks being effectively identical to those in Figure 22. Each of these drivers has an output level control block like those included with the line output drivers, allowing gain adjustment up to 9 dB on the output signal. As in the previous case, this output level adjustment is not intended to be used as a standard volume control, but instead is included for additional full-scale output signal-level control.

Figure 23. Architecture of the Output Stage Leading to the High-Power Output Drivers

The high-power output drivers include additional circuitry to avoid artifacts on the audio output during power-on and power-off transient conditions. First program the type of output configuration being used in register 14, page 0 to allow the device to select the optimal power-up scheme to avoid output artifacts. The power-up delay time for the high-power output drivers is also programmable over a wide range of time delays, from instantaneous up to 4 s, using register 42, page 0.

When powered down, place these output drivers into a variety of output conditions based on register programming. If lowest-power operation is desired, then the outputs can be placed into a high-impedance state and all power to the output stage is removed. However, this generally results in the output nodes drifting to rest near the upper or lower analog supply because of small leakage currents at the pins, which then results in a longer delay requirement to avoid output artifacts during driver power-on. In order to reduce this required power-on delay, the TLV320AIC3109-Q1 includes an option for the output pins of the drivers to be weakly driven to the VCM level that the pins normally rest at when powered with no signal applied. This output VCM level is determined by an internal band-gap voltage reference, and thus results in extra power dissipation when the drivers are in power down. However, this option provides the fastest method for transitioning the drivers from power-down to full-power operation without any output artifact introduced.

The device includes a further option that falls between the other two—although less power is required when the output drivers are in power down, a slightly longer delay is required to power up without artifacts than if the band-gap reference is kept alive. In this alternate mode, the powered-down output driver pin is weakly driven to a voltage of approximately half the DRVDD supply level using an internal voltage divider. This voltage does not match the actual VCM of a fully powered driver, but because of the output voltage being close to the final value, a much shorter power-up delay time setting can be used and still avoid any audible output artifacts. These output voltage options are controlled in page 0, register 42.

The high-power output drivers can also be programmed to power up first with the output level (gain) control in a highly attenuated state; then the output driver automatically reduces the output attenuation slowly to reach the programmed output gain. This capability is enabled by default but can be enabled in register 40, page 0.

7.3.8 Output Stage Volume Controls

A basic analog volume control with a range from 0 dB to –78 dB and mute is replicated multiple times in the output stage network, connected to each of the analog signals that route to the output stage. In addition, to enable completely independent mixing operations to be performed for each output driver, each analog signal coming into the output stage can have up to seven separate volume controls. These volume controls all have approximately 0.5-dB step programmability over most of the gain range, with steps increasing slightly at the lowest attenuations. Table 6 lists the detailed gain versus programmed setting for this basic volume control.

7.3.9 Input Impedance and VCM Control

The TLV320AIC3109-Q1 includes several programmable settings to control analog input pins, particularly when these inputs are not selected for connection to a PGA. The default option allows unselected inputs to be put into a high-impedance state such that the input impedance of the device is extremely high. However, the pins on the device do include protection diode circuits connected to AVDD and AVSS. Thus, if any voltage is driven onto a pin approximately one diode drop (~0.6 V) above AVDD or one diode drop below AVSS, these protection diodes begin conducting current, resulting in an effective impedance that no longer appears as a high-impedance state.

In most cases, ac-couple the analog input pins on the TLV320AIC3109-Q1 to the analog input sources, except if an ADC is used for dc voltage measurement. The ac-coupling capacitor causes a high-pass filter pole to be inserted into the analog signal path, so the size of the capacitor must be chosen to move that filter pole sufficiently low in frequency to cause minimal effect on the processed analog signal. The input impedance of the analog inputs when selected for connection to a PGA varies with the setting of the input level control, starting at approximately 20 kΩ with an input level control setting of 0 dB, and increasing to approximately 80 kΩ when the input level control is set at –12 dB. For example, using a 0.1-μF ac-coupling capacitor at an analog input results in a high-pass filter pole of 80 Hz when the 0-dB input level control setting is selected.

7.3.10 MICBIAS Generation

The TLV320AIC3109-Q1 includes a programmable microphone bias output voltage (MICBIAS), capable of providing output voltages of 2 V or 2.5 V (both derived from the on-chip, band-gap voltage) with a 4-mA output current drive. In addition, the MICBIAS can be programmed to be connected to AVDD directly through an on-chip switch, or powered down completely when not needed for power savings. This function is controlled by register programming in register 25, page 0.

7.3.11 Short-Circuit Output Protection

The TLV320AIC3109-Q1 includes programmable short-circuit protection for the high-power output drivers for maximum flexibility in a given application. By default, if shorted, these output drivers automatically limit the maximum amount of current that can be sourced to or sunk from a load, thereby protecting the device from an overcurrent condition. In this mode, register 95, page 0 can be read to determine whether the device is in short-circuit protection or not, and then the device can be programmed to power-down the output drivers if needed. However, the device includes further capability to power-down an output driver automatically whenever the driver goes into short-circuit protection without requiring user intervention. In this case, the output driver remains in a power-down condition until specifically programmed to power down and then power back up again to clear the short-circuit flag.

7.3.12 Jack and Headset Detection

The TLV320AIC3109-Q1 includes extensive capability to monitor a headphone, microphone, or headset jack, determine if a plug has been inserted into the jack, and then determine what type of headset or headphone is wired to the plug. Figure 24 shows one configuration of the device that enables detection and determination of headset type when a pseudo-differential (capacitor free) mono headphone output configuration is used. The registers used for this function are registers 14, 96, 97, and 13, page 0. The type of headset detected can be read back from register 13, page 0. For best results, select a MICBIAS value as high as possible and program the output driver common-mode level at a 1.35-V or 1.5-V level.

Figure 24. Configuration of Device for Jack Detection Using a Pseudo-Differential (Capacitor Free) Headphone Output Connection

Figure 25 shows a modified output configuration used when the output drivers are ac-coupled.

Figure 25. Configuration of Device for Jack Detection Using an AC-Coupled Mono Headphone Output Connection

7.4.1 Bypass Path Mode

The TLV320AIC3109-Q1 is a versatile device designed for low-power applications. In some cases, only a few features of the device are required. For these applications, the unused stages of the device must be powered down to save power and use an alternate route. This path is called a bypass path. The bypass path modes let the device save power by turning off unused stages (such as the ADC, DAC, and PGA).

7.4.1.2 Passive Analog Bypass During Power Down

Programming the TLV320AIC3109-Q1 to passive analog bypass occurs by configuring the output stage switches for passthrough. Figure 26 shows that this process is done by opening switches SW-L0, SW-L3, SW-R0, and SW-R3 and closing either SW-L1 and SW-R1. Programming this mode is done by writing to register 108, page 0.

Connecting the MIC1P/LINE1P input signal to the LEFT_LOP pin is done by closing SW-L1 and opening SW-L0; this action is done by writing a 1 to bit 0 in register 108, page 0. Connecting the MIC1M/LINE1M input signal to the LEFT_LOM pin is done by closing SW-L4 and opening SW-L3; this action is done by writing a 1 to bit 1 in register 108, page 0.

Connecting the MIC2P/LINE2P input signal to the RIGHT_LOP pin is done by closing SW-R1 and opening SW-R0; this action is done by writing a 1 to bit 4 in register 108, page 0. Figure 26 shows a diagram of the passive analog bypass mode configuration.

Figure 26. Passive Analog Bypass Mode Configuration

7.4.2 Digital Audio Processing for Record Path

In applications where record-only is selected and the DAC is powered down, the playback path signal processing blocks can be used in the ADC record path. These filtering blocks can support high-pass, low-pass, band-pass, or notch filtering. In this mode, the record-only path has switches SW-D1 and SW-D2 closed, and reroutes the ADC output data through the digital signal processing blocks. Because the DAC digital signal processing blocks are being re-used, naturally the addresses of these digital filter coefficients are the same as for the DAC digital processing and are located in registers 1–26, page 1. This record-only mode is enabled by powering down the DAC by writing to bit 7 in register 37, page 0 (where bit 7 = 0). Next, enable the digital filter pathway for the ADC by writing a 1 to bit 3 in register 107, page 0. (This pathway is only enabled if the DAC is powered down.) Figure 27 shows the record-only path.

Figure 27. Record-Only Mode With Digital Processing Path Enabled

7.5.1 I²C Control Interface

The TLV320AIC3109-Q1 supports the I²C control protocol using 7-bit addressing and is capable of both standard and fast modes. As illustrated in Figure 28, the minimum timing for each t_HD-STA, t_SU-STA, and t_SU-STO is 0.9 μs for I²C fast mode. The TLV320AIC3109-Q1 responds to the I²C address of 001 1000. I²C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I²C bus only drive the bus lines low by connecting the lines to ground; the devices never drive the bus lines high. Instead, the bus wires are pulled high by pullup resistors so the bus wires are high when not being driven low by a device. This way two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.

Figure 28. I²C Interface Timing

Communication on the I²C bus always takes place between two devices, one acting as the master and the other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of the master. Some I²C devices can act as masters or slaves, but the TLV320AIC3109-Q1 can only act as a slave device.

An I²C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data are transmitted across the I²C bus in groups of eight bits. To send a bit on the I²C bus, the SDA line is driven to the appropriate level when SCL is low (a low on SDA indicates the bit is zero; a high indicates the bit is one). When the SDA line settles, the SCL line is brought high then low. This pulse on SCL clocks the SDA bit into the receiver shift register.

The I²C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line. Under normal circumstances the master drives the clock line.

Most of the time the bus is idle, no communication is taking place, and both lines are high. When communication is taking place, the bus is active. Only master devices can start a communication by causing a START condition on the bus. Normally, the data line is only allowed to change state when the clock line is low. If the data line changes state when the clock line is high, then the data line state is either a START condition or a STOP condition. A START condition is when the clock line is high and the data line goes from high to low. A STOP condition is when the clock line is high and the data line goes from low to high.

After the master issues a START condition, the master sends a byte that indicates which slave device to communicate with. This byte is called the address byte. Each device on an I²C bus has a unique 7-bit address. (Slaves can also have 10-bit addresses; see the I²C specification for details.) The master sends an address in the address byte with a bit indicating whether to read from or write to the slave device.

Every byte transmitted on the I²C bus, address or data, is acknowledged with an acknowledge bit. When a master finishes sending a byte (eight data bits) to a slave, the master stops driving SDA and waits for the slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA low. The master then sends a clock pulse to clock the acknowledge bit. Similarly, when a master finishes reading a byte, the master pulls SDA low to acknowledge this operation to the slave. The master then sends a clock pulse to clock the bit.

A not-acknowledge is performed by simply leaving SDA high during an acknowledge cycle. If a device is not present on the bus and the master attempts to address the device, the master receives a not-acknowledge because no device is present at that address to pull the line low.

When a master finishes communicating with a slave, the master can issue a STOP condition. When a STOP condition is issued, the bus becomes idle again. A master can also issue another START condition. When a START condition is issued when the bus is active, this condition is called a repeated START condition.

The TLV320AIC3109-Q1 also responds to and acknowledges a general call, which consists of the master issuing a command with a slave-address byte of 00h. Figure 29 and Figure 30 show timing diagrams for I²C write and read operations, respectively.

Figure 29. I²C Write

Figure 30. I²C Read

In the case of an I²C register write, if the master does not issue a STOP condition, then the device enters auto-increment mode. So in the next eight clocks, the data on SDA are treated as data for the next incremental register.

Similarly, in the case of an I²C register read, after the device has sent out the 8-bit data from the addressed register, if the master issues an acknowledge, the slave takes over control of the SDA bus and transmits for the next 8 clocks the data of the next incremental register.

7.6.1 Register Map Structure

The register map of the TLV320AIC3109-Q1 consists of two pages of registers, with each page containing 128 registers. The register at address zero on each page is used as a page-control register and writing to this register determines the active page for the device. All subsequent read/write operations access the page that is active at the time unless a register write is performed to change the active page. The active page defaults to page 0 on device reset.

Table 7 lists the different access codes used in the TLV320AIC3109-Q1 registers.

The control registers for the TLV320AIC3109-Q1 are described in this section. All registers are 8 bits in width, with bit 7 referring to the most-significant bit of each register and bit 0 referring to the least-significant bit. Table 8 lists the registers for page 0 and page 1.

7.6.2 Page 0 Registers

These registers are held within page 0.