SLASE93A August   2017  – November 2017 TLV320AIC3109-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Audio Data Serial Interface Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Hardware Reset
      2. 7.3.2  Digital Audio Data Serial Interface
        1. 7.3.2.1 Right-Justified Mode
        2. 7.3.2.2 Left-Justified Mode
        3. 7.3.2.3 I2S Mode
        4. 7.3.2.4 DSP Mode
        5. 7.3.2.5 TDM Data Transfer
      3. 7.3.3  Audio Data Converters
        1. 7.3.3.1 Audio Clock Generation
        2. 7.3.3.2 Mono Audio ADC
          1. 7.3.3.2.1 Mono Audio ADC High-Pass Filter
          2. 7.3.3.2.2 Automatic Gain Control (AGC)
            1. 7.3.3.2.2.1 Target Level
            2. 7.3.3.2.2.2 Attack Time
            3. 7.3.3.2.2.3 Decay Time
            4. 7.3.3.2.2.4 Noise Gate Threshold
            5. 7.3.3.2.2.5 Maximum PGA Gain Applicable
      4. 7.3.4  Mono Audio DAC
        1. 7.3.4.1 Digital Audio Processing for Playback
        2. 7.3.4.2 Digital Interpolation Filter
        3. 7.3.4.3 Delta-Sigma Audio DAC
        4. 7.3.4.4 Audio DAC Digital Volume Control
        5. 7.3.4.5 Increasing DAC Dynamic Range
        6. 7.3.4.6 Analog Output Common-mode Adjustment
      5. 7.3.5  Audio Analog Inputs
      6. 7.3.6  Analog Fully Differential Line Output Drivers
      7. 7.3.7  Analog High-Power Output Drivers
      8. 7.3.8  Output Stage Volume Controls
      9. 7.3.9  Input Impedance and VCM Control
      10. 7.3.10 MICBIAS Generation
      11. 7.3.11 Short-Circuit Output Protection
      12. 7.3.12 Jack and Headset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bypass Path Mode
        1. 7.4.1.1 ADC PGA Signal Bypass Path Functionality
        2. 7.4.1.2 Passive Analog Bypass During Power Down
      2. 7.4.2 Digital Audio Processing for Record Path
    5. 7.5 Programming
      1. 7.5.1 I2C Control Interface
        1. 7.5.1.1 I2C Bus Debug in a Glitched System
    6. 7.6 Register Maps
      1. 7.6.1 Register Map Structure
      2. 7.6.2 Page 0 Registers
        1. 7.6.2.1  Register 0: Page Select (address = 0h) [reset = 0000 0000], Page 0
        2. 7.6.2.2  Register 1: Software Reset Register (address = 1h) [reset = 0000 0000], Page 0
        3. 7.6.2.3  Register 2: Codec Sample Rate Select Register (address = 2h) [reset = 0000 0000], Page 0
        4. 7.6.2.4  Register 3: PLL Programming Register A (address = 3h) [reset = 0001 0000], Page 0
        5. 7.6.2.5  Register 4: PLL Programming Register B (address = 4h) [reset = 0000 0100]
        6. 7.6.2.6  Register 5: PLL Programming Register C (address = 5h) [reset = 0000 0000], Page 0
        7. 7.6.2.7  Register 6: PLL Programming Register D (address = 6h) [reset = 0000 0000]
        8. 7.6.2.8  Register 7: Codec Data-Path Setup Register (address = 7h) [reset = 0000 0000], Page 0
        9. 7.6.2.9  Register 8: Audio Serial Data Interface Control Register A (address = 8h) [reset = 0000 0000], Page 0
        10. 7.6.2.10 Register 9: Audio Serial Data Interface Control Register B (address = 9h) [reset = 0000 0000], Page 0
        11. 7.6.2.11 Register 10: Audio Serial Data Interface Control Register C (address = Ah) [reset = 0000 0000], Page 0
        12. 7.6.2.12 Register 11: Audio Codec Overflow Flag Register (address = Bh) [reset = 0000 0001], Page 0
        13. 7.6.2.13 Register 12: Audio Codec Digital Filter Control Register (address = Ch) [reset = 0000 0000], Page 0
        14. 7.6.2.14 Register 13: Headset/Button Press Detection Register A (address = Dh) [reset = 0000 0000], Page 0
        15. 7.6.2.15 Register 14: Headset/Button Press Detection Register B (address = Eh) [reset = 0000 0000], Page 0
        16. 7.6.2.16 Register 15: ADC PGA Gain Control Register (address = Fh) [reset = 1000 0000], Page 0
        17. 7.6.2.17 Register 16: Auxiliary PGA Gain Control Register (address = Fh) [reset = 1000 0000], Page 0
        18. 7.6.2.18 Register 17-18: Reserved (address = 11h-12h) [reset = 1111 1111], Page 0
        19. 7.6.2.19 Register 19: MIC1P/LINE1P to ADC Control Register (address = 13h) [reset = 0111 1000], Page 0
        20. 7.6.2.20 Register 20: Reserved (address = 14h) [reset = 0111 1000], Page 0
        21. 7.6.2.21 Register 21: MIC2P/LINE2P to ADC Control Register (address = 15h) [reset = 0111 1000], Page 0
        22. 7.6.2.22 Registers 22-24: Reserved (address = 16h-18h) [reset = 0111 1000], Page 0
        23. 7.6.2.23 Register 25: MICBIAS Control Register (address = 25h) [reset = 0000 0110], Page 0
        24. 7.6.2.24 Register 26: AGC Control Register A (address = 1Ah) [reset = 0000 0000], Page 0
        25. 7.6.2.25 Register 27: AGC Control Register B (address = 1Bh) [reset = 1111 1110], Page 0
        26. 7.6.2.26 Register 28: AGC Control Register C (address = 1Ch) [reset = 0000 0000], Page 0
        27. 7.6.2.27 Register 29: Reserved (address = 1Dh) [reset = 0000 0000], Page 0
        28. 7.6.2.28 Register 30: Reserved (address = 1Eh) [reset = 1111 1110], Page 0
        29. 7.6.2.29 Register 31: Reserved (address = 1Fh) [reset = 0000 0000], Page 0
        30. 7.6.2.30 Register 32: AGC Gain Register (address = 20h) [reset = 1000 0000], Page 0
        31. 7.6.2.31 Register 33: Reserved (address = 21h) [reset = 0000 0000], Page 0
        32. 7.6.2.32 Register 34: AGC Noise Gate Debounce Register (address = 22h) [reset = 0000 0000], Page 0
        33. 7.6.2.33 Register 35: Reserved (address = 23h) [reset = 0000 0000], Page 0
        34. 7.6.2.34 Register 36: ADC Flag Register (address = 24h) [reset = 0000 0000], Page 0
        35. 7.6.2.35 Register 37: DAC Power and Output Driver Control Register (address = 25h) [reset = 0000 0000], Page 0
        36. 7.6.2.36 Register 38: High-Power Output Driver Control Register (address = 26h) [reset = 0000 0000], Page 0
        37. 7.6.2.37 Register 39: Reserved (address = 27h) [reset = 0000 0000], Page 0
        38. 7.6.2.38 Register 40: High-Power Output Stage Control Register (address = 28h) [reset = 0000 0000], Page 0
        39. 7.6.2.39 Register 41: DAC Output Switching Control Register (address = 29h) [reset = 0000 0000], Page 0
        40. 7.6.2.40 Register 42: Output Driver Pop Reduction Register (address = 2Ah) [reset = 0000 0000], Page 0
        41. 7.6.2.41 Register 43: DAC Digital Volume Control Register (address = 2Bh) [reset = 1000 0000], Page 0
        42. 7.6.2.42 Register 44: Reserved (address = 2Ch) [reset = 1000 0000], Page 0
        43. 7.6.2.43 Registers 45-50: Reserved (address = 2Dh-32h) [reset = 0000 0000], Page 0
        44. 7.6.2.44 Register 51: Reserved (address = 33h) [reset = 0000 0100], Page 0
        45. 7.6.2.45 Registers 52-57: Reserved (address = 34h-39h) [reset = 0000 0000], Page 0
        46. 7.6.2.46 Register 58: Reserved (address = 3Ah) [reset = 0000 0100], Page 0
        47. 7.6.2.47 Register 59: Reserved (address = 3Bh) [reset = 0000 0000], Page 0
        48. 7.6.2.48 Register 60: PGA to HPOUT Volume Control Register (address = 3Ch) [reset = 0000 0000], Page 0
        49. 7.6.2.49 Register 61: DAC_1 to HPOUT Volume Control Register (address = 3Dh) [reset = 0000 0000], Page 0
        50. 7.6.2.50 Register 62: Reserved Register (address = 3Eh) [reset = 0000 0000], Page 0
        51. 7.6.2.51 Register 63: PGA_AUX to HPOUT Volume Control Register (address = 3Fh) [reset = 0000 0000], Page 0
        52. 7.6.2.52 Register 64: Reserved (address = 40h) [reset = 0000 0000], Page 0
        53. 7.6.2.53 Register 65: HPOUT Output Level Control Register (address = 41h) [reset = 0000 0100], Page 0
        54. 7.6.2.54 Register 66: Reserved (address = 42h) [reset = 0000 0000], Page 0
        55. 7.6.2.55 Register 67: PGA to HPCOM Volume Control Register (address = 43h) [reset = 0000 0000], Page 0
        56. 7.6.2.56 Register 68: DAC_1 to HPCOM Volume Control Register (address = 44h) [reset = 0000 0000], Page 0
        57. 7.6.2.57 Register 69: Reserved (address = 45h) [reset = 0000 0000], Page 0
        58. 7.6.2.58 Register 70: PGA_AUX to HPCOM Volume Control Register (address = 46h) [reset = 0000 0000], Page 0
        59. 7.6.2.59 Register 71: Reserved (address = 47h) [reset = 0000 0000], Page 0
        60. 7.6.2.60 Register 72: HPCOM Output Level Control Register (address = 48h) [reset = 0000 0100], Page 0
        61. 7.6.2.61 Registers 73-80: Reserved (address = 49h-50h) [reset = 0000 0000], Page 0
        62. 7.6.2.62 Register 81: PGA to LEFT_LOP/M Volume Control Register (address = 51h) [reset = 0000 0000], Page 0
        63. 7.6.2.63 Register 82: DAC_1 to LEFT_LOP/M Volume Control Register (address = 52h) [reset = 0000 0000], Page 0
        64. 7.6.2.64 Register 83: Reserved (address = 53h) [reset = 0000 0000], Page 0
        65. 7.6.2.65 Register 84: PGA_AUX to LEFT_LOP/M Volume Control Register (address = 54h) [reset = 0000 0000], Page 0
        66. 7.6.2.66 Register 85: Reserved (address = 55h) [reset = 0000 0000], Page 0
        67. 7.6.2.67 Register 86: LEFT_LOP/M Output Level Control Register (address = 56h) [reset = 0000 0000], Page 0
        68. 7.6.2.68 Register 87: Reserved (address = 57h) [reset = 0000 0000], Page 0
        69. 7.6.2.69 Register 88: PGA to RIGHT_LOP/M Volume Control (address = 58h) [reset = 0000 0000], Page 0
        70. 7.6.2.70 Register 89: DAC_1 to RIGHT_LOP/M Volume Control (address = 59h) [reset = 0000 0000], Page 0
        71. 7.6.2.71 Register 90: Reserved (address = 5A) [reset = 0000 0000], Page 0
        72. 7.6.2.72 Register 91: PGA_AUX to RIGHT_LOP/M Volume Control (address = 5Bh) [reset = 0000 0000], Page 0
        73. 7.6.2.73 Register 92: Reserved (address = 5Ch) [reset = 0000 0000], Page 0
        74. 7.6.2.74 Register 93: RIGHT_LOP/M Output Level Control (address = 5Dh) [reset = 0000 0000], Page 0
        75. 7.6.2.75 Register 94: Module Power Status Register (address = 5Eh) [reset = 0000 0000], Page 0
        76. 7.6.2.76 Register 95: Output Driver Short-Circuit Detection Status Register (address = 5Fh) [reset = 0000 0000], Page 0
        77. 7.6.2.77 Register 96: Sticky Interrupt Flags Register (address = 60h) [reset = 0000 0000], Page 0
        78. 7.6.2.78 Register 97: Real-Time Interrupt Flags Register (address = 61h) [reset = 0000 0000], Page 0
        79. 7.6.2.79 Registers 98-100: Reserved (address = 62h-64h) [reset = 0000 0000], Page 0
        80. 7.6.2.80 Register 101: Clock Register (address = 65h) [reset = 0000 0000], Page 0
        81. 7.6.2.81 Register 102: Clock Generation Control Register (address = 66h) [reset = 0000 0000], Page 0
        82. 7.6.2.82 Register 103: AGC New Programmable Attack Time Register (address = 67h) [reset = 0000 0000], Page 0
        83. 7.6.2.83 Register 104: AGC New Programmable Decay Time Register (address = 68h) [reset = 0000 0000], Page 0
        84. 7.6.2.84 Registers 105-106: Reserved (address = 69h-6Ah) [reset = 0000 0000], Page 0
        85. 7.6.2.85 Register 107: New Programmable ADC Digital Path and I2C Bus Condition Register (address = 6Bh) [reset = 0000 0000], Page 0
        86. 7.6.2.86 Register 108: Passive Analog Signal Bypass Selection During Power Down Register (address = 6Ch) [reset = 0000 0000], Page 0
        87. 7.6.2.87 Register 109: DAC Quiescent Current Adjustment Register (address = 6Dh) [reset = 0000 0000], Page 0
        88. 7.6.2.88 Registers 110-127: Reserved (address = 6Eh-7Fh) [reset = 0000 0000], Page 0
      3. 7.6.3 Page 1 Register Descriptions
        1. 7.6.3.1  Register 0: Page Select Register (address = 0h) [reset = 0000 0000], Page 1
        2. 7.6.3.2  Register 1: Audio Effects Filter N0 Coefficient MSB Register (address = 1h) [reset = 0110 1011], Page 1
        3. 7.6.3.3  Register 2: Audio Effects Filter N0 Coefficient LSB Register (address = 2h) [reset = 1110 0011], Page 1
        4. 7.6.3.4  Register 3: Audio Effects Filter N1 Coefficient MSB Register (address = 3h) [reset = 1001 0110], Page 1
        5. 7.6.3.5  Register 4: Audio Effects Filter N1 Coefficient LSB Register (address = 4h) [reset = 0110 0110], Page 1
        6. 7.6.3.6  Register 5: Audio Effects Filter N2 Coefficient MSB Register (address = 5h) [reset = 0110 0111], Page 1
        7. 7.6.3.7  Register 6: Audio Effects Filter N2 Coefficient LSB Register (address = 6h) [reset = 0101 1101], Page 1
        8. 7.6.3.8  Register 7: Audio Effects Filter N3 Coefficient MSB Register (address = 7h) [reset = 0110 1011], Page 1
        9. 7.6.3.9  Register 8: Audio Effects Filter N3 Coefficient LSB Register (address = 8h) [reset = 1110 0011], Page 1
        10. 7.6.3.10 Register 9: Audio Effects Filter N4 Coefficient MSB Register (address = 9h) [reset = 1001 0110], Page 1
        11. 7.6.3.11 Register 10: Audio Effects Filter N4 Coefficient LSB Register (address = Ah) [reset = 0110 0110], Page 1
        12. 7.6.3.12 Register 11: Audio Effects Filter N5 Coefficient MSB Register (address = Bh) [reset = 0110 0111], Page 1
        13. 7.6.3.13 Register 12: Audio Effects Filter N5 Coefficient LSB Register (address = Ch) [reset = 0101 1101], Page 1
        14. 7.6.3.14 Register 13: Audio Effects Filter D1 Coefficient MSB Register (address = Dh) [reset = 0111 1101], Page 1
        15. 7.6.3.15 Register 14: Audio Effects Filter D1 Coefficient LSB Register (address = Eh) [reset = 1000 0011h], Page 1
        16. 7.6.3.16 Register 15: Audio Effects Filter D2 Coefficient MSB Register (address = Fh) [reset = 1000 0100], Page 1
        17. 7.6.3.17 Register 16: Audio Effects Filter D2 Coefficient LSB Register (address = 10h) [reset = 1110 1110], Page 1
        18. 7.6.3.18 Register 17: Audio Effects Filter D4 Coefficient MSB Register (address = 11h) [reset = 0111 1101], Page 1
        19. 7.6.3.19 Register 18: Audio Effects Filter D4 Coefficient LSB Register (address = 12h) [reset = 1000 0011], Page 1
        20. 7.6.3.20 Register 19: Audio Effects Filter D5 Coefficient MSB Register (address = 13h) [reset = 1000 0100], Page 1
        21. 7.6.3.21 Register 20: Audio Effects Filter D5 Coefficient LSB Register (address = 14h) [reset = 1110 1110], Page 1
        22. 7.6.3.22 Register 21: De-Emphasis Filter N0 Coefficient MSB Register (address = 15h) [reset = 0011 1001], Page 1
        23. 7.6.3.23 Register 22: De-Emphasis Filter N0 Coefficient LSB Register (address = 16h) [reset = 0101 0101], Page 1
        24. 7.6.3.24 Register 23: De-Emphasis Filter N1 Coefficient MSB Register (address = 17h) [reset = 1111 0011], Page 1
        25. 7.6.3.25 Register 24: De-Emphasis Filter N1 Coefficient LSB Register (address = 18h) [reset = 0010 1101], Page 1
        26. 7.6.3.26 Register 25: De-Emphasis Filter D1 Coefficient MSB Register (address = 19h) [reset = 0101 0011], Page 1
        27. 7.6.3.27 Register 26: De-Emphasis Filter D1 Coefficient LSB Register (address = 1Ah) [reset = 0111 1110], Page 1
        28. 7.6.3.28 Register 27: Reserved (address = 1Bh) [reset = 0110 1011], Page 1
        29. 7.6.3.29 Register 28: Reserved (address = 1Ch) [reset = 1110 0011], Page 1
        30. 7.6.3.30 Register 29: Reserved (address = 1Dh) [reset = 1001 0110], Page 1
        31. 7.6.3.31 Register 30: Reserved (address = 1Eh) [reset = 0110 0110], Page 1
        32. 7.6.3.32 Register 31: Reserved (address = 1Fh) [reset = 0110 0111], Page 1
        33. 7.6.3.33 Register 32: Reserved (address = 20h) [reset = 0101 1101], Page 1
        34. 7.6.3.34 Register 33: Reserved (address = 21h) [reset = 0110 1011], Page 1
        35. 7.6.3.35 Register 34: Reserved (address = 22h) [reset = 1110 0011], Page 1
        36. 7.6.3.36 Register 35: Reserved (address = 23h) [reset = 1001 0110], Page 1
        37. 7.6.3.37 Register 36: Reserved (address = 24h) [reset = 0110 0110], Page 1
        38. 7.6.3.38 Register 37: Reserved (address = 25h) [reset = 0110 0111], Page 1
        39. 7.6.3.39 Register 38: Reserved (address = 26h) [reset = 0101 1101], Page 1
        40. 7.6.3.40 Register 39: Reserved (address = 27h) [reset = 0111 1101], Page 1
        41. 7.6.3.41 Register 40: Reserved (address = 28h) [reset = 1000 0011], Page 1
        42. 7.6.3.42 Register 41: Reserved (address = 29h) [reset = 1000 0100], Page 1
        43. 7.6.3.43 Register 42: Reserved (address = 2Ah) [reset = 1110 1110], Page 1
        44. 7.6.3.44 Register 43: Reserved (address = 2Bh) [reset = 0111 1101], Page 1
        45. 7.6.3.45 Register 44: Reserved (address = 2Ch) [reset = 1000 0011], Page 1
        46. 7.6.3.46 Register 45: Reserved (address = 2Dh) [reset = 1000 0100], Page 1
        47. 7.6.3.47 Register 46: Reserved (address = 2Eh) [reset = 1110 1110], Page 1
        48. 7.6.3.48 Register 47: Reserved (address = 2Fh) [reset = 0011 1001], Page 1
        49. 7.6.3.49 Register 48: Reserved (address = 30h) [reset = 0101 0101], Page 1
        50. 7.6.3.50 Register 49: Reserved (address = 31h) [reset = 1111 0011], Page 1
        51. 7.6.3.51 Register 50: Reserved (address = 32h) [reset = 0010 1101], Page 1
        52. 7.6.3.52 Register 51: Reserved (address = 33h) [reset = 0101 0011], Page 1
        53. 7.6.3.53 Register 52: Reserved (address = 34h) [reset = 0111 1110], Page 1
        54. 7.6.3.54 Register 53: Reserved (address = 35h) [reset = 0111 1111], Page 1
        55. 7.6.3.55 Register 54: Reserved (address = 36h) [reset = 1111 1111], Page 1
        56. 7.6.3.56 Registers 55-64: Reserved (address = 37h-40h) [reset = 0000 0000], Page 1
        57. 7.6.3.57 Register 65: ADC High-Pass Filter N0 Coefficient MSB Register (address = 41h) [reset = 0011 1001], Page 1
        58. 7.6.3.58 Register 66: ADC High-Pass Filter N0 Coefficient LSB Register (address = 42h) [reset = 1110 1010], Page 1
        59. 7.6.3.59 Register 67: Channel ADC High-Pass Filter N1 Coefficient MSB Register (address = 43h) [reset = 1000 0000 , Page 1
        60. 7.6.3.60 Register 68: Channel ADC High-Pass Filter N1 Coefficient LSB Register (address = 44h) [reset = 0001 0110], Page 1
        61. 7.6.3.61 Register 69: Channel ADC High-Pass Filter D1 Coefficient MSB Register (address = 45h) [reset = 0111 1111], Page 1
        62. 7.6.3.62 Register 70: Channel ADC High-Pass Filter D1 Coefficient LSB Register (address = 46h) [reset = 1101 0101], Page 1
        63. 7.6.3.63 Register 71: Reserved (address = 47h) [reset = 0111 1111], Page 1
        64. 7.6.3.64 Register 72: Reserved (address = 48h) [reset = 1110 1010], Page 1
        65. 7.6.3.65 Register 73: Reserved (address = 49h) [reset = 1000 0000], Page 1
        66. 7.6.3.66 Register 74: Reserved (address = 4Ah) [reset = 0001 0110], Page 1
        67. 7.6.3.67 Register 75: Reserved (address = 4Bh) [reset = 0111 1111], Page 1
        68. 7.6.3.68 Register 76: Reserved (address = 4Ch) [reset = 1101 0101], Page 1
        69. 7.6.3.69 Registers 77h-127h: Reserved (address = 4Dh) [reset = 0000 0000], Page 1
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

(1)(2)
MIN MAX UNIT
Power-supply voltage AVDD to AVSS, DRVDD to DRVSS –0.3 3.9 V
AVDD to DRVSS –0.3 3.9
IOVDD to DVSS –0.3 3.9
DVDD to DVSS –0.3 2.5
AVDD to DRVDD –0.1 0.1
Analog input voltage Analog input voltage to AVSS –0.3 AVDD + 0.3 V
Digital input voltage Digital input voltage to DVSS –0.3 IOVDD + 0.3 V
Temperature Operating ambient, TA –40 105 °C
Junction, TJ –40 125
Storage, Tstg –40 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) ESD compliance tested to EIA/JESD22-A114-B and passed.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
Charged-device model (CDM),
per AEC Q100-011		 Corner pins
(1, 8, 9, 16,17, 24, 25, 32)		 ±750
All other pins ±500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
POWER SUPPLY
Analog supply voltage (AVDD to AVSS, DRVDD to DRVSS) 2.7 3.3 3.6 V
Digital core supply voltage (DVDD to DVSS) 1.525 1.8 1.95 V
Digital I/O supply voltage (IOVDD to DVSS) 1.1 1.8 3.6 V
ANALOG INPUTS
VI Analog full-scale, 0-dB input voltage (DRVDD = 3.3 V) 0.707 VRMS
DIGITAL INPUTS
VDIG Digital input voltage DVSS IOVDD V
TEMPERATURE
TA Operating free-air temperature –40 105 °C
OTHERS
Mono line output load resistance 10 kΩ
Mono headphone output load resistance 16 Ω
Digital output load capacitance 10 pF

6.4 Thermal Information

THERMAL METRIC(1) TLV320AIC3109-Q1 UNIT
RHB (VQFN) RHM (VQFN)
32 PINS 32 PINS
RθJA Junction-to-ambient thermal resistance 31.1 31.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 19.5 18.9 °C/W
RθJB Junction-to-board thermal resistance 10.6 11.1 °C/W
ψJT Junction-to-top characterization parameter 0.2 0.2 °C/W
ψJB Junction-to-board characterization parameter 10.6 11.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 0.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

at 25°C, AVDD = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, and 16-bit audio data (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUDIO ADC
Input signal level Single-ended configurations 0.707 VRMS
SNR Signal-to-noise ratio(1)(2) A-weighted, fS = 48 kSPS, 0-dB PGA gain,
inputs ac-shorted to ground		 80 92 dB
DR Dynamic range(1)(2) fS = 48 kSPS; 0-dB PGA gain; 1-kHz, –60-dB,
full-scale input signal		 93 dB
THD Total harmonic distortion fS = 48 kSPS; 0-dB PGA gain; 1-kHz, –2-dB,
full-scale input signal		 –89 –75 dB
PSRR Power-supply rejection ratio 217-Hz signal applied to DRVDD 55 dB
1-kHz signal applied to DRVDD 44
Input channel separation 1-kHz, –2-dB, full-scale signal, MIC1 to MIC2 –71 dB
Gain error fS = 48 kSPS; 0-dB PGA gain; 1-kHz, –2-dB,
full-scale input signal		 0.82 dB
ADC programmable-gain amplifier maximum gain 1-kHz input tone 59.5 dB
ADC programmable-gain amplifier step size 0.5 dB
Input resistance MIC1/MIC2 inputs routed to single ADC
input MIX attenuation = 0 dB		 20 kΩ
MIC1/MIC2 inputs routed to single ADC
input MIX attenuation = 12 dB		 80
Input resistance 80 kΩ
Input capacitance MIC1/LINE1 inputs 10 pF
Input level control minimum attenuation setting 0 dB
Input level control maximum attenuation setting 12 dB
Input level control attenuation step size 1.5 dB
ANALOG PASSTHROUGH MODE
RDS(on) Input-to-output switch resistance MIC1/LINE1 to LINEOUT 330 Ω
INPUT SIGNAL LEVEL, DIFFERENTIAL
SNR Signal-to-noise ratio A-weighted, fS = 48 kSPS, 0-dB PGA gain,
inputs ac-shorted to ground		 92 dB
THD Total harmonic distortion fS = 48 kHz; 0-dB PGA gain, 1-kHz, –2-dB,
full-scale input signal		 –94 dB
ADC DIGITAL DECIMATION FILTER (fS = 48 kHz)
Filter gain From 0 fS to 0.39 fS ±0.1 dB
At 0.4125 fS –0.25
At 0.45 fS –3
At 0.5 fS –17.5
From 0.55 fS to 64 fS –75
Filter group delay 17/fS s
MICROPHONE BIAS
Bias voltage Programmable setting = 2 V 2 V
Programmable setting = 2.5 V 2.3 2.455 2.7
Programmable setting = AVDD AVDD
Current sourcing Programmable setting = 2.5 V 4 mA
AUDIO DAC, DIFFERENTIAL LINE OUTPUT (RLOAD = 10 kΩ)
Full-scale output voltage 0-dB input full-scale signal, output common-mode setting = 1.35 V, output volume control = 0 dB 1.414 VRMS
4 VPP
SNR Signal-to-noise ratio(3) A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal, referenced to full-scale input level 88 102 dB
DR Dynamic range A-weighted, fS = 48 kHz, –60-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V 97 dB
THD Total harmonic distortion fS = 48 kHz; 0-dB, 1-kHz input full-scale signal; output volume control = 0 dB; output common-mode setting = 1.35 V –95 –75 dB
PSRR Power-supply rejection ratio 217-Hz signal applied to DRVDD, AVDD 78 dB
1-kHz signal applied to DRVDD, AVDD 80
DAC gain error 0-dB, 1-kHz input full-scale signal; output volume control = 0 dB; output common-mode setting = 1.35 V; fS = 48 kHz –0.2 dB
AUDIO DAC, SINGLE-ENDED LINE OUTPUT (RLOAD = 10 kΩ)
Full-scale output voltage 0-dB input full-scale signal, output common-mode setting = 1.35 V, output volume control = 0 dB 0.707 VRMS
SNR Signal-to-noise ratio A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal, referenced to full-scale input level 96 dB
A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal, referenced to full-scale input level, 50% DAC current-boost mode 97
DR Dynamic range A-weighted, fS = 48 kHz, –60-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V 91 dB
DAC gain error 0-dB, 1-kHz input full-scale signal; output volume control = 0 dB; output common-mode setting = 1.35 V; fS = 48 kHz –0.85 dB
AUDIO DAC, SINGLE-ENDED HEADPHONE OUTPUT (RLOAD = 16 Ω)
Full-scale output voltage 0-dB input full-scale signal, output common-mode setting = 1.35 V, output volume control = 0 dB 0.707 VRMS
SNR Signal-to-noise ratio A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal, referenced to full-scale input level 96 dB
A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal, referenced to full-scale input level, 50% DAC current-boost mode 97
DR Dynamic range A-weighted, fS = 48 kHz, –60-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V 91 dB
THD Total harmonic distortion fS = 48 kHz, 0-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V –71 –65 dB
PSRR Power-supply rejection ratio 217-Hz signal applied to DRVDD, AVDD 43 dB
1-kHz signal applied to DRVDD, AVDD 41
DAC gain error 0-dB, 1-kHz input full-scale signal; output volume control = 0 dB; output common-mode setting = 1.35 V; fS = 48 kHz –0.85 dB
DAC DIGITAL INTERPOLATION FILTER (fS = 48 kHz)
Pass band 0 0.45 fS Hz
Pass-band ripple ±0.06 dB
Transition band 0.45 fS 0.55 fS Hz
Stop band 0.55 fS 7.5 fS Hz
Stop-band attenuation 65 dB
Group delay 21 / fS s
MONO HEADPHONE DRIVER (AC-Coupled Output Configuration(3))
0-dB full-scale output voltage 0-dB gain to high-power outputs, output common-mode voltage setting = 1.35 V 0.707 VRMS
Programmable output common-mode voltage (applicable to line outputs also) First option 1.35 V
Second option 1.5
Third option 1.65
Fourth option 1.8
Maximum programmable output level control gain 9 dB
Programmable output level control gain step size 1 dB
PO Maximum output power RL = 32 Ω 15 mW
RL = 16 Ω 30
SNR Signal-to-noise ratio(4) A-weighted 94 dB
MONO HEADPHONE DRIVER (AC-Coupled Output Configuration, continued)
THD Total harmonic distortion 1-kHz output, PO = 5 mW, RL = 32 Ω –77 dB
0.014%
1-kHz output, PO = 10 mW, RL = 32 Ω –76 dB
0.016%
1-kHz output, PO = 10 mW, RL = 16 Ω –73 dB
0.022%
1-kHz output, PO = 20 mW, RL = 16 Ω –71 dB
0.028%
Channel separation 1-kHz, 0-dB input 90 dB
PSRR Power-supply rejection ratio 217 Hz, 100 mVPP on AVDD, DRVDD 48 dB
Mute attenuation 1-kHz output 107 dB
DIGITAL I/O
VIL Input low level –0.3 0.3 IOVDD V
VIH Input high level(5) IOVDD > 1.6 V 0.7 IOVDD V
IOVDD ≤ 1.6 V 1.1
VOL Output low level 0.1 IOVDD V
VOH Output high level 0.8 IOVDD V
CURRENT CONSUMPTION (DRVDD = AVDD = IOVDD = 3.3 V, DVDD = 1.8 V)
IIN IDRVDD + IAVDD RESET held low 0.1 µA
IDVDD 0.2
IDRVDD + IAVDD Mono ADC record, fS = 8 kSPS, I2S slave,
AGC off, no signal		 2.15 mA
IDVDD 0.48
IDRVDD + IAVDD Mono ADC record, fS = 48 kSPS, I2S slave,
AGC off, no signal		 4.31(6)
IDVDD 2.45(6)
IDRVDD + IAVDD Mono DAC playback to lineout, analog mixer bypassed, fS = 48 kSPS, I2S slave 3.5
IDVDD 2.3
IDRVDD + IAVDD Mono DAC playback to lineout, fS = 48 kSPS,
I2S slave, no signal		 4.9
IDVDD 2.3
IDRVDD + IAVDD Mono DAC playback to mono single-ended headphone, fS = 48 kSPS, I2S slave, no signal 6.7
IDVDD 2.3
IDRVDD + IAVDD Mono line in to mono line out, no signal 3.11
IDVDD 0
IDRVDD + IAVDD Extra power when PLL enabled 1.4
IDVDD 0.9
IDRVDD + IAVDD All blocks powered down, headset detection enabled, headset not inserted 28 µA
IDVDD 2
(1) Ratio of output level with 1-kHz, full-scale, sine-wave input to the output level with the inputs short-circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz, low-pass filter and an A-weighted filter, where noted. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) Unless otherwise noted, all measurements use an output common-mode voltage setting of 1.35 V, a 0-dB output level control gain, and a 16-Ω single-ended load.
(4) Ratio of output level with a 1-kHz, full-scale input to the output level playing an all-zero signal, measured A-weighted over a 20-Hz to
20-kHz bandwidth.
(5) When IOVDD < 1.6 V, minimum VIH is 1.1 V.
(6) Additional power is consumed when the PLL is powered.

6.6 Audio Data Serial Interface Timing Requirements(1)(2)

IOVDD = 1.1 V IOVDD = 3.3 V UNIT
MIN MAX MIN MAX
I2S, LEFT-JUSTIFIED AND RIGHT-JUSTIFIED TIMING IN MASTER MODE (See Figure 1)
td(WS) ADWS, WCLK delay time 50 15 ns
td(DO-WS) ADWS, WCLK to DOUT delay time 50 20 ns
td(DO-BCLK) BCLK to DOUT delay time 50 15 ns
ts(DI) DIN setup time 10 6 ns
th(DI) DIN hold time 10 6 ns
tr Rise time 30 10 ns
tf Fall time 30 10 ns
DSP TIMING IN MASTER MODE (See Figure 2)
td(WS) ADWS, WCLK delay time 50 15 ns
td(DO-BCLK) BCLK to DOUT delay time 50 15 ns
ts(DI) DIN setup time 10 6 ns
th(DI) DIN hold time 10 6 ns
tr Rise time 30 10 ns
tf Fall time 30 10 ns
I2S, LEFT-JUSTIFIED AND RIGHT-JUSTIFIED TIMING IN SLAVE MODE (See Figure 3)
tH(BCLK) BCLK high period 70 35 ns
tL(BCLK) BCLK low period 70 35 ns
ts(WS) ADWS, WCLK setup time 10 6 ns
th(WS) ADWS, WCLK hold time 10 6 ns
td(DO-WS) ADWS, WCLK to DOUT delay time (for left-justified mode only) 50 35 ns
td(DO-BCLK) BCLK to DOUT delay time 50 20 ns
ts(DI) DIN setup time 10 6 ns
th(DI) DIN hold time 10 6 ns
tr Rise time 8 4 ns
tf Fall time 8 4 ns
DSP TIMING IN SLAVE MODE (See Figure 4)
tH(BCLK) BCLK high period 70 35 ns
tL(BCLK) BCLK low period 70 35 ns
ts(WS) ADWS, WCLK setup time 10 8 ns
th(WS) ADWS, WCLK hold time 10 8 ns
td(DO-BCLK) BCLK to DOUT delay time 50 20 ns
ts(DI) DIN setup time 10 6 ns
th(DI) DIN hold time 10 6 ns
tr Rise time 8 4 ns
tf Fall time 8 4 ns
(1) All timing specifications are measured at characterization but not tested at final test.
(2) All specifications at 25°C, DVDD = 1.8 V.
TLV320AIC3109-Q1 t0145-01_las510.gif Figure 1. I2S, Left-Justified and Right-Justified Format Timing in Master Mode
TLV320AIC3109-Q1 t0146-01_las510.gif Figure 2. DSP Timing in Master Mode
TLV320AIC3109-Q1 t0145-02_las510.gif Figure 3. I2S, Left-Justified and Right-Justified Format Timing in Slave Mode
TLV320AIC3109-Q1 t0146-02_las510.gif Figure 4. DSP Timing in Slave Mode

6.7 Typical Characteristics

at 25°C, AVDD = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, and 16-bit audio data (unless otherwise noted)
TLV320AIC3109-Q1 g001_las520.gif
Load = 16 Ω, ac-coupled
Figure 5. THD vs Headphone Power, 16-Ω Load
TLV320AIC3109-Q1 g004_las520.gif
Figure 7. Line Input to ADC FFT Plot
TLV320AIC3109-Q1 g009_slase93.gif
Figure 9. ADC Gain Error vs PGA Gain Setting
TLV320AIC3109-Q1 g008_las520.gif
Figure 11. MICBIAS Output Voltage vs Ambient Temperature
TLV320AIC3109-Q1 g003_las520.gif
Figure 6. DAC to Line Output FFT Plot
TLV320AIC3109-Q1 g006_las520.gif
Input = –65 dBFS
Figure 8. ADC SNR vs PGA Gain Setting, –65-dBFS Input
TLV320AIC3109-Q1 g007_las520.gif
Figure 10. MICBIAS Output Voltage vs AVDD