SBOS757 May 2016 TLV2369 , TLV369


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information: TLV369
    5. 6.5Thermal Information: TLV2369
    6. 6.6Electrical Characteristics
    7. 6.7Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1Operating Voltage
      2. 7.3.2Input Common-Mode Voltage Range
      3. 7.3.3Protecting Inputs from Overvoltage
    4. 7.4Device Functional Modes
  8. Application and Implementation
    1. 8.1Application Information
    2. 8.2Typical Application
      1. 8.2.1Design Requirements
      2. 8.2.2Detailed Design Procedure
      3. 8.2.3Application Curve
    3. 8.3System Examples
      1. 8.3.1Battery Monitoring
      2. 8.3.2Window Comparator
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Documentation Support
      1. 11.1.1Related Documentation
        1. Links
    2. 11.2Community Resources
    3. 11.3Trademarks
    4. 11.4Electrostatic Discharge Caution
    5. 11.5Glossary
  12. 12Mechanical, Packaging, and Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
VoltageSupply, VS = (V+) – (V–)0+7V
Signal input pin(2)(V–) – 0.5(V+) + 0.5V
CurrentSignal input pin(2)–1010mA
Output short-circuit(3)ContinuousmA
Temperature Operating, TA –40125°C
Junction, TJ150°C
Storage, Tstg–65150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less.
(3) Short-circuit to VS / 2, one amplifier per package.

6.2 ESD Ratings

over operating free-air temperature range (unless otherwise noted).
V(ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted).
VSSupply voltage1.85.5V
Specified temperature–4085°C

6.4 Thermal Information: TLV369

DCK (SC70)
RθJAJunction-to-ambient thermal resistance 293.3°C/W
RθJC(top)Junction-to-case (top) thermal resistance 95.2°C/W
RθJBJunction-to-board thermal resistance 83.4°C/W
ψJTJunction-to-top characterization parameter 2.9°C/W
ψJBJunction-to-board characterization parameter 82.4°C/W
RθJC(bot)Junction-to-case (bottom) thermal resistance n/a°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Thermal Information: TLV2369

RθJAJunction-to-ambient thermal resistance 121.5168.5°C/W
RθJC(top)Junction-to-case (top) thermal resistance 66.358.1°C/W
RθJBJunction-to-board thermal resistance 62.588.9°C/W
ψJTJunction-to-top characterization parameter 22.89.3°C/W
ψJBJunction-to-board characterization parameter 61.987.6°C/W
RθJC(bot)Junction-to-case (bottom) thermal resistance n/an/a°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.6 Electrical Characteristics

VS (total supply voltage) = 1.8 V to 5.5 V; at TA = 25°C, and RL = 100 kΩ connected to VS / 2 (unless otherwise noted)
VOSInput offset voltageAt TA= 25°C0.42mV
At TA = –40°C to +85°C0.85
dVOS/dTDriftAt TA = –40°C to +85°C0.5μV/°C
PSRRPower-supply rejection ratioVS = 1.8 V to 5.5 V8094dB
VCM Common-mode voltage rangeVV+ V
CMRRCommon-mode rejection ratio(V–) ≤ VCM ≤ (V+)80110dB
IBInput bias currentAt TA= 25°C10pA
At TA= –40°C to +85°CSee Figure 8
IOSInput offset current10pA
ZIDDifferential1013 || 3Ω || pF
ZICCommon-mode1013 || 6Ω || pF
EnInput voltage noisef = 0.1 Hz to 10 Hz4μVPP
enInput voltage noise densityf = 1 kHz300nV/√Hz
inInput current noise densityf = 1 kHz1fA/√Hz
AOLOpen-loop voltage gainAt VS = 5.5 V, 100 mV ≤ VO ≤ (V+) – 100 mV,
RL = 100 kΩ
At VS = 5.5 V, 500 mV ≤ VO ≤ (V+) – 500 mV,
RL = 10 kΩ
VOVoltage output swing from railRL = 10 kΩ25mV
ISCShort-circuit current10mA
CLOADCapacitive load drive See Figure 10
GBPGain bandwidth product12kHz
SRSlew rateG = 10.005V/µs
tOR Overload recovery timeVIN  × gain = VS 250µs
VSSpecified voltage range1.85.5V
IQQuiescent current IO = 0 mA, at VS = 5.5 V8001300nA
Specified range–4085°C
TAOperating range–40125°C

6.7 Typical Characteristics

at TA = 25°C, VS = 5 V, and RL = 100 kΩ connected to VS / 2 (unless otherwise noted)
TLV369 TLV2369 tc_normal-cmvltg_bos757.gif
10 typical units shown, VS = 5 V
Figure 1. Normalized Offset Voltage vs
Common-Mode Voltage
TLV369 TLV2369 tc_open-loop_gain_phase_bos757.gif
VS = 5.5 V
Figure 3. Open-Loop Gain and Phase vs Frequency
TLV369 TLV2369 tc_cm_rej_ratio-freq_bos757.gif
Figure 5. Common-Mode Rejection Ratio vs Frequency
TLV369 TLV2369 tc_max_out_vltg-freq_bos757.gif
Figure 7. Maximum Output Voltage vs Frequency
TLV369 TLV2369 tpc_open-loop-freq_bos757.gif
Figure 9. Open-Loop Output Impedance vs Frequency
TLV369 TLV2369 tc_scope_resp_sm20_bos757.gif
CL = 20 pF
Figure 11. Small-Signal Step Response
TLV369 TLV2369 tc_overload_scope_bos757.gif
Figure 13. Overload Recovery
TLV369 TLV2369 tc_scope_noise_bos757.gif
Figure 2. 0.1-Hz to 10-Hz Noise
TLV369 TLV2369 tc_open_loop_gain_temp_bos757.gif
Figure 4. Open-Loop Gain vs Temperature
TLV369 TLV2369 tc_output_vltg_swing-tmp_bos757.gif
Figure 6. Output Voltage Swing from Rail vs Temperature
TLV369 TLV2369 tc_inputbc-tmp_bos757.gif
Figure 8. Input Bias Current vs Temperature
TLV369 TLV2369 tc_ss_overshoot_bos757.gif
Figure 10. Small-Signal Overshoot vs Capacitive Load
TLV369 TLV2369 tc_scope_resp_lrg_bos757.gif
Figure 12. Large-Signal Step Response