TMS320C5545 Fixed-Point Digital Signal Processor |

This product is in the process of being discontinued. Customers may still purchase limited quantities by contacting their TI sales representative or authorized distributor. Please review TI’s obsolescence policy for details on placing final orders and receiving final shipments.
Fixed-Point Digital Signal Processor



These devices are members of TI's C5000 fixed-point digital signal processor (DSP) product family and are designed for low-power applications.

The fixed-point DSP is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and power savings. The CPU supports an internal bus structure composed of one program bus, one 32-bit data read bus, two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels that provide data movement for 16 independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, both in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-and-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic and logic unit (ALU) is supported by an additional 16-bit ALU. Used under instruction set control, the ALUs provide the ability to optimize parallel activity and power consumption. These resources are managed in the address unit (AU) and data unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The instruction unit (IU) fetches 32-bit program from internal or external memory and queues instructions for the program unit (PU). The PU decodes the instructions, directs tasks to the AU and DU resources, and manages the fully protected pipeline. Predictive branching avoids pipeline flushes when conditional instructions execute.

The GPIO functions, along with the 10-bit SAR ADC, provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial media is supported through two secure digital (SD) peripherals, four Inter-IC Sound (I2S Bus) modules, one serial port interface (SPI) with up to three chip selects, one Inter-Integrated Circuit (I2C) multimaster and slave interface, and a universal asynchronous receiver/transmitter (UART) interface.

Additional peripherals include: a high-speed universal serial bus (USB 2.0) device mode only, a real-time clock (RTC), three general-purpose (GP) timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.

In addition, the device includes a tightly coupled FFT hardware accelerator. The tightly coupled FFT hardware accelerator supports 8- to 1024-point (in power of 2) real and complex-valued FFTs.

Furthermore, the device includes the following three integrated LDOs to power different sections of the device:

ANA_LDO provides 1.3 V to the DSP PLL (VDDA_PLL), SAR, and power-management circuits (VDDA_ANA).

DSP_LDO provides 1.3 V or 1.05 V to the DSP core (CVDD), selectable on-the-fly by software as long as operating frequency ranges are observed.

USB_LDO provides 1.3 V to the USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3).

These devices are supported by the industry’s award-winning eXpressDSP, Code Composer Studio Integrated Development Environment (IDE), DSP/BIOS, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX, XDS100, XDS510, XDS560 emulation device drivers, and evaluation modules. The devices are also supported by the C55x DSP library, which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) and chip support libraries.


  • Core:
    • High-Performance, Low-Power, TMS320C55x Fixed-Point Digital Signal Processor
      • 16.67-, 10-, 8.33-ns Instruction Cycle Time
      • 60-, 100-, 120-MHz Clock Rate
      • One or Two Instructions Executed per Cycle
      • Dual Multiply-and-Accumulate (MAC) Units (up to 200 or 240 Million Multiply-Accumulates per Second [MMACS])
      • Two Arithmetic and Logic Units (ALUs)
      • Three Internal Data and Operand Read Buses and Two Internal Data and Operand Write Buses
      • Software-Compatible With C55x Devices
      • Industrial Temperature Devices Available
    • 320KB of Zero-Wait State On-Chip RAM, Composed of:
      • 64KB of Dual-Access RAM (DARAM), 8 Blocks of 4K × 16-Bit
      • 256KB of Single-Access RAM (SARAM),
        32 Blocks of 4K × 16-Bit
    • 128KB of Zero Wait-State On-Chip ROM
      (4 Blocks of 16K x 16-Bit)
    • Tightly Coupled Fast Fourier transform (FFT) Hardware Accelerator
  • Peripheral:
    • Direct Memory Access (DMA) Controller
      • Four DMA With 4 Channels Each (16 Channels Total)
    • Three 32-Bit General-Purpose (GP) Timers
      • One Selectable as a Watchdog or GP
    • Two Embedded Multimedia Card (eMMC) or Secure Digital (SD) Interfaces
    • Universal Asynchronous Receiver/Transmitter (UART)
    • Serial Port Interface (SPI) With Three Chip Selects
    • Master and Slave Inter-Integrated Circuit (I2C Bus)
    • Four Inter-IC Sound (I2S Bus) for Data Transport
    • Device USB Port With Integrated 2.0 High-Speed PHY That Supports:
      • USB 2.0 Full- and High-Speed Device
    • LCD Bridge With Asynchronous Interface
    • 10-Bit 3-Input Successive Approximation (SAR) Analog-to-Digital Converter (ADC)
    • IEEE 1149.1 (JTAG)
    • 32 General-Purpose I/O (GPIO) Pins
      (Multiplexed With Other Device Functions)
      • Configure up to 20 GPIO Pins at the Same Time
  • Power:
    • Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
    • Three I/O Isolated Power Supply Domains: RTC I/O, USB PHY, and DVDDIO
    • Three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to Power the Isolated Domains: DSP Core, Analog, and USB Core, Respectively
    • 1.05-V Core (60 MHz), 1.8-, 2.5-, 2.75-, or 3.3-V I/Os
    • 1.3-V Core (100 or 120 MHz), 1.8-, 2.5-, 2.75-, or 3.3-V I/Os
  • Clock:
    • External Clock Source Through CLKIN Pin That Supports 11.2896-, 12.000-, and 12.288-MHz Clock Frequencies
    • Real-Time Clock (RTC) With 32.768-kHz Crystal Input, Separate Clock Domain, and Separate Power Supply
    • Low-Power, Software-Programmable Phase-Locked Loop (PLL) Clock Generator
  • Bootloader:
    • On-Chip ROM Bootloader (RBL) to Boot From SPI EEPROM, SPI Serial Flash or I2C EEPROM eMMC, SD, SDHC, UART, and USB
  • Package:
    • 118-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZQW Suffix)

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Part number Order DSP DRAM USB SPI UART (SCI) Serial I/O Rating Operating temperature range (C) I2C Approx. price (US$) Operating systems
TMS320C5532 Order now 1 C55x     SDRAM       1     1     I2C
Catalog     -10 to 70
-40 to 85    
1     1.97 | 1ku     DSP/BIOS
TMS320C5533 Samples not available 1 C55x     SDRAM     1     1     1     I2C
Catalog     -10 to 70
-40 to 85    
1     2.21 | 1ku     DSP/BIOS
TMS320C5534 Samples not available 1 C55x     SDRAM     1     1     1     I2C
Catalog     -10 to 70
-40 to 85    
1     2.47 | 1ku     DSP/BIOS
TMS320C5535 Samples not available 1 C55x     SDRAM     1     1     1     I2C
Catalog     -10 to 70
-40 to 85    
1     2.71 | 1ku     DSP/BIOS