SPRS377F September 2008  – June 2014 TMS320C6745 , TMS320C6747


  1. 1 TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagram
  2. 2Revision History
  3. 3Device Overview
    1. 3.1Device Characteristics
    2. 3.2Device Compatibility
    3. 3.3DSP Subsystem
      1. 3.3.1C674x DSP CPU Description
      2. 3.3.2DSP Memory Mapping
        1. Memories
        2. Internal Memories
        3. CPU
    4. 3.4Memory Map Summary
    5. 3.5Pin Assignments
      1. 3.5.1 Pin Map (Bottom View)
    6. 3.6Terminal Functions
      1. 3.6.1  Device Reset and JTAG
      2. 3.6.2  High-Frequency Oscillator and PLL
      3. 3.6.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.6.4  External Memory Interface A (ASYNC, SDRAM)
      5. 3.6.5  External Memory Interface B (only SDRAM)
      6. 3.6.6  Serial Peripheral Interface Modules (SPI0, SPI1)
      7. 3.6.7  Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
      8. 3.6.8  Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
      9. 3.6.9  Enhanced Quadrature Encoder Pulse Module (eQEP)
      10. 3.6.10 Boot
      11. 3.6.11Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      12. 3.6.12Inter-Integrated Circuit Modules (I2C0, I2C1)
      13. 3.6.13Timers
      14. 3.6.14 Universal Host-Port Interface (UHPI)
      15. 3.6.15Multichannel Audio Serial Ports (McASP0, McASP1, McASP2)
      16. 3.6.16Universal Serial Bus Modules (USB0, USB1)
      17. 3.6.17Ethernet Media Access Controller (EMAC)
      18. 3.6.18Multimedia Card/Secure Digital (MMC/SD)
      19. 3.6.19 Liquid Crystal Display Controller (LCD)
      20. 3.6.20General Purpose Input Output (GPIO)
      21. 3.6.21Reserved and No Connect
      22. 3.6.22Supply and Ground
      23. 3.6.23Unused USB0 (USB2.0) and USB1 (USB1.1) Pin Configurations
  4. 4Device Configuration
    1. 4.1Boot Modes
    2. 4.2SYSCFG Module
    3. 4.3Pullup/Pulldown Resistors
    4. 4.4Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)
    5. 4.5Handling Ratings
    6. 4.6Recommended Operating Conditions
    7. 4.7Notes on Recommended Power-On Hours (POH)
    8. 4.8Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
  5. 5Peripheral Information and Electrical Specifications
    1. 5.1 Parameter Information
      1. 5.1.1Parameter Information Device-Specific Information
        1. Transition Levels
    2. 5.2 Recommended Clock and Control Signal Transition Behavior
    3. 5.3 Power Supplies
      1. 5.3.1Power-on Sequence
      2. 5.3.2Power-off Sequence
    4. 5.4 Reset
      1. 5.4.1Power-On Reset (POR)
      2. 5.4.2Warm Reset
      3. 5.4.3Reset Electrical Data Timings
    5. 5.5 Crystal Oscillator or External Clock Input
    6. 5.6 Clock PLLs
      1. 5.6.1PLL Device-Specific Information
      2. 5.6.2Device Clock Generation
      3. 5.6.3PLL Controller 0 Registers
    7. 5.7 Interrupts
      1. 5.7.1DSP Interrupts
    8. 5.8 General-Purpose Input/Output (GPIO)
      1. 5.8.1GPIO Register Description(s)
      2. 5.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
      3. 5.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
    9. 5.9 EDMA
    10. 5.10External Memory Interface A (EMIFA)
      1. 5.10.1EMIFA Asynchronous Memory Support
      2. 5.10.2EMIFA Synchronous DRAM Memory Support
      3. 5.10.3EMIFA SDRAM Loading Limitations
      4. 5.10.4EMIFA Connection Examples
      5. 5.10.5External Memory Interface A (EMIFA) Registers
      6. 5.10.6EMIFA Electrical Data/Timing
    11. 5.11External Memory Interface B (EMIFB)
      1. 5.11.1EMIFB SDRAM Loading Limitations
      2. 5.11.2Interfacing to SDRAM
      3. 5.11.3EMIFB Electrical Data/Timing
    12. 5.12Memory Protection Units
    13. 5.13MMC / SD / SDIO (MMCSD)
      1. 5.13.1MMCSD Peripheral Description
      2. 5.13.2 MMCSD Peripheral Register Description(s)
      3. 5.13.3MMC/SD Electrical Data/Timing
    14. 5.14Ethernet Media Access Controller (EMAC)
      1. 5.14.1 EMAC Peripheral Register Description(s)
    15. 5.15Management Data Input/Output (MDIO)
      1. 5.15.1MDIO Registers
      2. 5.15.2Management Data Input/Output (MDIO) Electrical Data/Timing
    16. 5.16Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)
      1. 5.16.1McASP Peripheral Registers Description(s)
      2. 5.16.2McASP Electrical Data/Timing
        1. Audio Serial Port 0 (McASP0) Timing
        2. Audio Serial Port 1 (McASP1) Timing
        3. Audio Serial Port 2 (McASP2) Timing
    17. 5.17Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 5.17.1SPI Peripheral Registers Description(s)
      2. 5.17.2SPI Electrical Data/Timing
        1. Peripheral Interface (SPI) Timing
    18. 5.18Enhanced Capture (eCAP) Peripheral
    19. 5.19Enhanced Quadrature Encoder (eQEP) Peripheral
    20. 5.20Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 5.20.1Enhanced Pulse Width Modulator (eHRPWM) Timing
      2. 5.20.2Trip-Zone Input Timing
    21. 5.21LCD Controller
      1. 5.21.1LCD Interface Display Driver (LIDD Mode)
      2. 5.21.2LCD Raster Mode
    22. 5.22Timers
      1. 5.22.1Timer Electrical Data/Timing
    23. 5.23Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
      1. 5.23.1I2C Device-Specific Information
      2. 5.23.2I2C Peripheral Registers Description(s)
      3. 5.23.3I2C Electrical Data/Timing
        1. Circuit (I2C) Timing
    24. 5.24 Universal Asynchronous Receiver/Transmitter (UART)
      1. 5.24.1UART Peripheral Registers Description(s)
      2. 5.24.2UART Electrical Data/Timing
    25. 5.25USB1 Host Controller Registers (USB1.1 OHCI)
      1. 5.25.1USB1 Unused Signal Configuration
    26. 5.26USB0 OTG (USB2.0 OTG)
      1. 5.26.1USB2.0 Electrical Data/Timing
      2. 5.26.2USB0 Unused Signal Configuration
    27. 5.27Host-Port Interface (UHPI)
      1. 5.27.1HPI Device-Specific Information
      2. 5.27.2HPI Peripheral Register Description(s)
      3. 5.27.3HPI Electrical Data/Timing
    28. 5.28Power and Sleep Controller (PSC)
      1. 5.28.1Power Domain and Module Topology
        1. Domain States
        2. States
    29. 5.29Programmable Real-Time Unit Subsystem (PRUSS)
      1. 5.29.1PRUSS Register Descriptions
    30. 5.30Emulation Logic
      1. 5.30.1JTAG Port Description
      2. 5.30.2Scan Chain Configuration Parameters
      3. 5.30.3JTAG 1149.1 Boundary Scan Considerations
    31. 5.31IEEE 1149.1 JTAG
      1. 5.31.1 JTAG Peripheral Register Description(s) - JTAG ID Register (DEVIDR0)
      2. 5.31.2 JTAG Test-Port Electrical Data/Timing
    32. 5.32Real Time Clock (RTC)
      1. 5.32.1Clock Source
      2. 5.32.2Real-Time Clock Registers
  6. 6Device and Documentation Support
    1. 6.1Device Support
      1. 6.1.1Development Support
      2. 6.1.2Device and Development-Support Tool Nomenclature
    2. 6.2Documentation Support
    3. 6.3Community Resources
    4. 6.4Related Links
    5. 6.5Trademarks
    6. 6.6Electrostatic Discharge Caution
    7. 6.7Glossary
  7. 7Mechanical Packaging and Orderable Information
    1. 7.1Thermal Data for ZKB
    2. 7.2Thermal Data for PTP
    3. 7.3Supplementary Information About the 176-pin PTP PowerPAD™ Package
      1. 7.3.1Standoff Height
      2. 7.3.2PowerPAD™ PCB Footprint
    4. 7.4Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZKB|256
Orderable Information

1 TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor

1.1 Features

  • Software Support
    • TI DSP/BIOS™
    • Chip Support Library and DSP Library
  • 375- and 456-MHz TMS320C674x VLIW DSP
  • C674x Instruction Set Features
    • Superset of the C67x+ and C64x+ ISAs
    • Up to 3648 MIPS and 2736 MFLOPS C674x
    • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two-Level Cache Memory Architecture
    • 32KB of L1P Program RAM/Cache
    • 32KB of L1D Data RAM/Cache
    • 256KB of L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Transfer Controllers
    • 32 Independent DMA Channels
    • 8 Quick DMA Channels
    • Programmable Transfer Burst Size
  • TMS320C674x Fixed- and Floating-Point VLIW DSP Core
    • Load-Store Architecture with Nonaligned Support
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32- and 40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
      • Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating Point Multiply Supported up to:
        • 2 SP x SP -> SP Per Clock
        • 2 SP x SP -> DP Every Two Clocks
        • 2 SP x DP -> DP Every Three Clocks
        • 2 DP x DP -> DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Hardware Support for Modulo Loop
    • Protected Mode Operation
    • Exceptions Support for Error Detection and Program Redirection
  • 128KB of RAM Shared Memory (TMS320C6747 Only)
  • 3.3-V LVCMOS I/Os (Except for USB Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space (TMS320C6747 Only)
    • EMIFB
      • 32-Bit or 16-Bit SDRAM with 256-MB Address Space (TMS320C6747)
      • 16-Bit SDRAM with 128-MB Address Space (TMS320C6745)
  • Three Configurable 16550-Type UART Modules:
    • UART0 with Modem Control Signals
    • Autoflow Control Signals (CTS, RTS) on UART0 Only
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • LCD Controller (TMS320C6747 Only)
  • Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
  • Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
  • Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
  • One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth (TMS320C6747 Only)
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Realtime Unit (PRU) Cores
      • 32-Bit Load and Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled via Software to Save Power
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • USB 1.1 OHCI (Host) with Integrated PHY (USB1) (TMS320C6747 Only)
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client (TMS320C6747)
    • USB 2.0 Full-Speed Client (TMS320C6745)
    • USB 2.0 High-, Full-, and Low-Speed Host (TMS320C6747)
    • USB 2.0 Full- and Low-Speed Host (TMS320C6745)
    • High-Speed Functionality Available on TMS320C6747 Device Only
    • End Point 0 (Control)
    • End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
  • Three Multichannel Audio Serial Ports (McASPs):
    • TMS320C6747 Supports 3 McASPs
    • TMS320C6745 Supports 2 McASPs
    • Six Clock Zones and 28 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable (McASP2)
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • RMII Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Real-Time Clock with 32-kHz Oscillator and Separate Power Rail (TMS320C6747 Only)
  • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Three Enhanced Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
    • 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Time-Stamps
  • Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • TMS320C6747 Device:
    • 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
  • TMS320C6745 Device:
    • 176-pin PowerPAD™ Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch
  • Commercial, Industrial, Extended, or Automotive Temperature

1.2 Applications

  • A/V Receivers
  • Automotive Amplifiers
  • Soundbars
  • Home Theatre Systems
  • Professional Audio
  • Network Streaming Audio

1.3 Description

The TMS320C6745/6747 device is a low-power digital signal processor based on a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The TMS320C6745/6747 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring high processing performance .

The TMS320C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128KB of RAM shared memory (TMS320C6747 only) is available for use by other hosts without affecting DSP performance.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial ports (McASPs) with 16/9 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI) [TMS320C6747 only]; up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the TMS320C6745/6747 device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

Device Information(1)

TMS320C6745HLQFP (176)24.00 mm x 24.00 mm
TMS320C6747BGA (256) 17.00 mm x 17.00 mm
(1) For more information on these devices, see Section 7, Mechanical Packaging and Orderable Information.

1.4 Functional Block Diagram

Note: Not all peripherals are available at the same time due to multiplexing. See Table 3-1 for details on which device components are available on each device.
Figure 1-1 TMS320C6747 Functional Block Diagram

Note: Not all peripherals are available at the same time due to multiplexing. See Table 3-1 for details on which device components are available on each device.
Figure 1-2 TMS320C6745 Functional Block Diagram