TMS320F28055 Piccolo™ 32-bit MCU with 60 MHz, 128 KB Flash, CLA, PGAs | TI.com

TMS320F28055 (ACTIVE) Piccolo™ 32-bit MCU with 60 MHz, 128 KB Flash, CLA, PGAs

Piccolo™ 32-bit MCU with 60 MHz, 128 KB Flash, CLA, PGAs - TMS320F28055
Datasheet
TMS320F2805x Piccolo™ Microcontrollers datasheet (Rev. C)
Errata
 

Description

TMS320C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-loop performance in real-time control applications. The C2000™ microcontrollers line includes the Delfino™ Premium Performance microcontroller family and the Piccolo™ Entry Performance microcontroller family.

The F2805x Piccolo™ family of microcontrollers (MCUs) provides the power of the C28x core and CLA coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration.

An internal voltage regulator allows for single-rail operation. Analog comparators with internal 6-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead and latency.

The Analog Front End (AFE) contains up to seven comparators with up to three integrated DACs, one VREFOUT-buffered DAC, up to four PGAs, and up to four digital filters. The PGAs can amplify the input signal in three discrete gain modes. The actual number of AFE peripherals will depend upon the TMS320F2805x device number. See Device Comparison for more details.

Features

  • High-Efficiency 32-Bit CPU (TMS320C28x)
    • 60 MHz (16.67-ns Cycle Time)
    • 16 × 16 and 32 × 32 Multiply and Accumulate (MAC) Operations
    • 16 × 16 Dual MAC
    • Harvard Bus Architecture
    • Atomic Operations
    • Fast Interrupt Response and Processing
    • Unified Memory Programming Model
    • Code-Efficient (in C/C++ and Assembly)
  • Programmable Control Law Accelerator (CLA)
    • 32-Bit Floating-Point Math Accelerator
    • Executes Code Independently of the Main CPU
  • Dual-Zone Security Module
  • Endianness: Little Endian
  • Low Device and System Cost:
    • Single 3.3-V Supply
    • No Power Sequencing Requirement
    • Integrated Power-on Reset and Brownout Reset
    • Low Power
    • No Analog Support Pins
  • Clocking:
    • Two Internal Zero-Pin Oscillators
    • On-Chip Crystal Oscillator and External Clock Input
    • Watchdog Timer Module
    • Missing Clock Detection Circuitry
  • Up to 42 Individually Programmable, Multiplexed General-Purpose Input/Output (GPIO) Pins With Input Filtering
  • JTAG Boundary Scan Support
    • IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture
  • Peripheral Interrupt Expansion (PIE) Block That Supports All Peripheral Interrupts
  • Three 32-Bit CPU Timers
  • Independent 16-Bit Timer in Each ePWM Module
  • On-Chip Memory
    • Flash, SARAM, Message RAM, OTP, CLA Data ROM, Boot ROM, Secure ROM Available
  • 128-Bit Security Key and Lock
    • Protects Secure Memory Blocks
    • Prevents Firmware Reverse Engineering
  • Serial Port Peripherals
    • Three Serial Communications Interface (SCI) (Universal Asynchronous Receiver/Transmitter [UART]) Modules
    • One Serial Peripheral Interface (SPI) Module
    • One Inter-Integrated-Circuit (I2C) Bus
    • One Enhanced Controller Area Network (eCAN) Bus
  • Enhanced Control Peripherals
    • Enhanced Pulse Width Modulator (ePWM)
    • Enhanced Capture (eCAP) Module
    • Enhanced Quadrature Encoder Pulse (eQEP) Module
  • Analog Peripherals
    • One 12-Bit Analog-to-Digital Converter (ADC)
    • One On-Chip Temperature Sensor for Oscillator Compensation
    • Up to Seven Comparators With up to Three Integrated Digital-to-Analog Converters (DACs)
    • One Buffered Reference DAC
    • Up to Four Programmable Gain Amplifiers (PGAs)
    • Up to Four Digital Filters
  • Advanced Emulation Features
    • Analysis and Breakpoint Functions
    • Real-Time Debug Through Hardware
  • 80-Pin PN Low-Profile Quad Flatpack (LQFP)
  • Temperature Options
    • T: –40°C to 105°C
    • S: –40°C to 125°C
    • Q: –40°C to 125°C
      (AEC Q100 Qualification for Automotive Applications)

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Parametrics

Compare all products in Piccolo entry performance MCUs Email Download to Excel
Part number Order Features CPU Total processing (MIPS) Frequency (MHz) Flash (KB) RAM (KB) ADC resolution ADC (Ch) PGA/VGA Comparators (#) Sigma-delta filter PWM (Ch) High-resolution PWM (ch) QEP PM bus I2C SPI CAN (#) UART (SCI) USB Operating temperature range (C) Analog-to-digital converter (ADC) CAP DAC channels Frequency per CLA (MHz) GPIO Package size: mm2:W x L (PKG) Processing accelerators PWM technology type ROM (KB) Temp sensor
TMS320F28055 Order now AEC Q100     C28x
CLA    		 120     60     128     20     12-bit     16     4     7     0     14     0     1     0     1     1     1     3     0     -40 to 125
-40 to 105    		 ADC12: 2-S/H, 3.75-MSPS     1     0     60     42     80LQFP: 196 mm2: 14 x 14 (LQFP | 80)         Type 1     0     0    
TMS320F28050 Samples not available AEC Q100     C28x     60     60     32     12     12-bit     16     3     6     0     14     0     1     0     1     1     1     3     0     -40 to 125     ADC12: 2-S/H, 2-MSPS     1     0