TMS320VC5420 Digital Signal Processor | TI.com

TMS320VC5420 (NRND) Digital Signal Processor

 

Not Recommended for New Designs (NRND)

Replaced By OMAP-L137 – The device has SIMILAR FUNCTIONALITY but is not functionally equivalent to the compared device.

TI does not recommend using this part in a new design. This product continues to be in production to support existing customers.

Description

The TMS320VC5420 fixed-point digital signal processor (DSP) is a dual CPU device capable of up to 200-MIPS performance. The 5420 consists of two independent 54x subsystems capable of core-to-core communications.

Each subsystem CPU is based on an advanced, modified Harvard architecture that has one program memory bus and three data memory buses. The processor also provides an arithmetic logic unit (ALU) that has a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

Each subsystem has separate program and data spaces, allowing simultaneous accesses to program instructions and data. Two read operations and one write operation can be performed in one cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. Furthermore, data can be transferred between program and data spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit manipulation operations that can be performed in a single machine cycle. In addition, the 5420 includes the control mechanisms to manage interrupts, repeated operations, and function calls.

The 5420 is offered in two temperature ranges and individual part numbers as shown below. (Please note that the industrial temperature device part numbers do not follow the typical numbering tradition.)

Commercial temperature devices (0°C to 100°C)
TMS320VC5420PGE200 (144-pin LQFP)
TMS320VC5420GGU200 (144-pin BGA)

Industrial temperature range devices (-40°C to 100°C)
TMS320C5420PGEA200 (144-pin LQFP)
TMS320C5420GGUA200 (144-pin BGA)

Features

  • 200-MIPS Dual-Core DSP Consisting of Two Independent Subsystems
  • Each Core Has an Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Bus
  • 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel-Shifter and Two 40-Bit Accumulators Per Core
  • Each Core Has a 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operations
  • Each Core Has a Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
  • Each Core Has an Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
  • Each Core Has Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
  • 16-Bit Data Bus With Data Bus Holder Feature
  • 256K × 16 Extended Program Address Space
  • Total of 192K × 16 Dual- and Single-Access On-Chip RAM
  • Single-Instruction Repeat and Block-Repeat Operations
  • Instructions With 32-Bit Long Word Operands
  • Instructions With 2 or 3 Operand Reads
  • Fast Return From Interrupts
  • Arithmetic Instructions With Parallel Store and Parallel Load
  • Conditional Store Instructions
  • Output Control of CLKOUT
  • Output Control of TOUT
  • Power Consumption Control With IDLE1,IDLE2, and IDLE3 Instructions
  • Dual 1.8-V (Core) and 3.3-V (I/O) Power Supplies for Low Power, Fast Operation
  • 10-ns Single-Cycle Fixed-Point Instruction Execution
  • Interprocessor Communication via Two Internal 8-Element FIFOs
  • 12 Channels of Direct Memory Access (DMA) for Data Transfers With No CPU Loading (6 Channels Per Subsystem)
  • Six Multichannel Buffered Serial Ports (McBSPs) (Three McBSPs Per Subsystem)
  • 16-Bit Host-Port Interface (HPI16) Multiplexed With External Memory Interface Pins
  • Software-Programmable Phase-Locked Loop (PLL) Provides Several Clocking Options (Requires External TTL Oscillator)
  • On-Chip Scan-Based Emulation Logic
  • Two Software-Programmable Timers (One Per Subsystem)
  • Software-Programmable Wait-State Generator (14 Wait States Maximum)
  • Provided in 144-pin BGA Ball Grid Array (GGU Suffix) and 144-pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix) Packages

TMS320C54x is a trademark of Texas Instruments.
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