SPNS164C April 2012  – April 2015 TMS570LS2125 , TMS570LS2135 , TMS570LS3135


  1. 1Device Overview
    1. 1.1Features
    2. 1.2Applications
    3. 1.3Description
    4. 1.4Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1PGE QFP Package Pinout (144-Pin)
    2. 4.2ZWT BGA Package Ball-Map (337-Ball Grid Array)
    3. 4.3Terminal Functions
      1. 4.3.1PGE Package
        1. Multibuffered Analog-to-Digital Converters (MibADCs)
        2. Enhanced High-End Timer (N2HET) Modules
        3. General-Purpose Input/Output (GPIO)
        4. FlexRay Interface Controller (FlexRay)
        5. Controller Area Network Controllers (DCANs)
        6. Local Interconnect Network Interface Module (LIN)
        7. Standard Serial Communication Interface (SCI)
        8. Inter-Integrated Circuit Interface Module (I2C)
        9. Standard Serial Peripheral Interface (SPI)
        10. Serial Peripheral Interface Modules (MibSPI)
        11. Module Interface
        12. Inputs and Outputs
        13. and Debug Modules Interface
        14. Supply and Test Pads
        15. for Core Logic: 1.2-V Nominal
        16. for I/O Cells: 3.3-V Nominal
        17. Reference for All Supplies Except VCCAD
      2. 4.3.2ZWT Package
        1. Multibuffered Analog-to-Digital Converters (MibADCs)
        2. Enhanced High-End Timer (N2HET) Modules
        3. General-Purpose Input/Output (GPIO)
        4. FlexRay Interface Controller (FlexRay)
        5. Controller Area Network Controllers (DCANs)
        6. Local Interconnect Network Interface Module (LIN)
        7. Standard Serial Communication Interface (SCI)
        8. Inter-Integrated Circuit Interface Module (I2C)
        9. Standard Serial Peripheral Interface (SPI)
        10. Serial Peripheral Interface Modules (MibSPI)
        11. Memory Interface (EMIF)
        12. Trace Macrocell for Cortex-R4F CPU (ETM-R4F)
        13. Trace Port (RTP)
        14. Modification Module (DMM)
        15. Module Interface
        16. Inputs and Outputs
        17. and Debug Modules Interface
        18. Supply and Test Pads
        19. Connects
        20. for Core Logic: 1.2-V Nominal
        21. for I/O Cells: 3.3-V Nominal
        22. Reference for All Supplies Except VCCAD
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Switching Characteristics for Clock Domains
    6. 5.6 Wait States Required
    7. 5.7 Power Consumption
    8. 5.8 Input/Output Electrical Characteristics
    9. 5.9 Thermal Resistance Characteristics
    10. 5.10Output Buffer Drive Strengths
    11. 5.11Input Timings
    12. 5.12Output Timings
    13. 5.13Low-EMI Output Buffers
  6. 6System Information and Electrical Specifications
    1. 6.1 Device Power Domains
    2. 6.2 Voltage Monitor Characteristics
      1. 6.2.1Important Considerations
      2. 6.2.2Voltage Monitor Operation
      3. 6.2.3Supply Filtering
    3. 6.3 Power Sequencing and Power On Reset
      1. 6.3.1Power-Up Sequence
      2. 6.3.2Power-Down Sequence
      3. 6.3.3Power-On Reset: nPORRST
        1. Electrical and Timing Requirements
    4. 6.4 Warm Reset (nRST)
      1. 6.4.1Causes of Warm Reset
      2. 6.4.2nRST Timing Requirements
    5. 6.5 ARM-R4F CPU Information
      1. 6.5.1Summary of ARM Cortex-R4F CPU Features
      2. 6.5.2ARM Cortex-R4F CPU Features Enabled by Software
      3. 6.5.3Dual Core Implementation
      4. 6.5.4Duplicate Clock Tree After GCLK
      5. 6.5.5ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety
      6. 6.5.6CPU Self-Test
        1. Sequence for CPU Self-Test
        2. Self-Test Clock Configuration
        3. Self-Test Coverage
    6. 6.6 Clocks
      1. 6.6.1Clock Sources
        1. Oscillator
          1. Requirements for Main Oscillator
        2. Power Oscillator
          2. Electrical and Timing Specifications
        3. Locked Loop (PLL) Clock Modules
          1. Diagram
          2. Timing Specifications
        4. Clock Inputs
      2. 6.6.2Clock Domains
        1. Domain Descriptions
        2. of Clock Domains to Device Modules
      3. 6.6.3Clock Test Mode
    7. 6.7 Clock Monitoring
      1. 6.7.1Clock Monitor Timings
      2. 6.7.2External Clock (ECLK) Output Functionality
      3. 6.7.3Dual Clock Comparators
        2. of DCC Clock Source Inputs
    8. 6.8 Glitch Filters
    9. 6.9 Device Memory Map
      1. 6.9.1Memory Map Diagram
      2. 6.9.2Memory Map Table
      3. 6.9.3Master/Slave Access Privileges
        1. Notes on Accesses to Certain Slaves
      4. 6.9.4POM Overlay Considerations
    10. 6.10Flash Memory
      1. 6.10.1Flash Memory Configuration
      2. 6.10.2Main Features of Flash Module
      3. 6.10.3ECC Protection for Flash Accesses
      4. 6.10.4Flash Access Speeds
      5. 6.10.5Flash Program and Erase Timings for Program Flash
      6. 6.10.6Flash Program and Erase Timings for Data Flash
    11. 6.11Tightly Coupled RAM (TCRAM) Interface Module
      1. 6.11.1Features
      2. 6.11.2TCRAM Interface ECC Support
    12. 6.12 Parity Protection for Peripheral RAMs
    13. 6.13On-Chip SRAM Initialization and Testing
      1. 6.13.1On-Chip SRAM Self-Test Using PBIST
        2. RAM Groups
      2. 6.13.2On-Chip SRAM Auto Initialization
    14. 6.14External Memory Interface (EMIF)
      1. 6.14.1Features
      2. 6.14.2Electrical and Timing Specifications
        1. RAM
        2. Timing
    15. 6.15Vectored Interrupt Manager
      1. 6.15.1VIM Features
      2. 6.15.2Interrupt Request Assignments
    16. 6.16DMA Controller
      1. 6.16.1DMA Features
      2. 6.16.2Default DMA Request Map
    17. 6.17Real Time Interrupt Module
      1. 6.17.1Features
      2. 6.17.2Block Diagrams
      3. 6.17.3Clock Source Options
      4. 6.17.4Network Time Synchronization Inputs
    18. 6.18Error Signaling Module
      1. 6.18.1Features
      2. 6.18.2ESM Channel Assignments
    19. 6.19Reset / Abort / Error Sources
    20. 6.20Digital Windowed Watchdog
    21. 6.21Debug Subsystem
      1. 6.21.1 Block Diagram
      2. 6.21.2 Debug Components Memory Map
      3. 6.21.3 JTAG Identification Code
      4. 6.21.4 Debug ROM
      5. 6.21.5 JTAG Scan Interface Timings
      6. 6.21.6 Advanced JTAG Security Module
      7. 6.21.7 Embedded Trace Macrocell (ETM-R4)
        1. TRACECLKIN Selection
        2. Specifications
      8. 6.21.8 RAM Trace Port (RTP)
        2. Specifications
      9. 6.21.9 Data Modification Module (DMM)
        2. Specifications
      10. 6.21.10Boundary Scan Chain
  7. 7Peripheral Information and Electrical Specifications
    1. 7.1 Peripheral Legend
    2. 7.2 Multibuffered 12-Bit Analog-to-Digital Converter
      1. 7.2.1Features
      2. 7.2.2Event Trigger Options
        1. MIBADC1 Event Trigger Hookup
        2. MIBADC1 Event Trigger Hookup
        3. MIBADC2 Event Trigger Hookup
        4. MIBADC2 Event Trigger Hookup
      3. 7.2.3ADC Electrical and Timing Specifications
      4. 7.2.4Performance (Accuracy) Specifications
        1. Nonlinearity Errors
        2. Total Error
    3. 7.3 General-Purpose Input/Output
      1. 7.3.1Features
    4. 7.4 Enhanced High-End Timer (N2HET)
      1. 7.4.1Features
      2. 7.4.2N2HET RAM Organization
      3. 7.4.3Input Timing Specifications
      4. 7.4.4N2HET1-N2HET2 Interconnections
      5. 7.4.5N2HET Checking
        1. Monitoring
        2. Monitoring Using Dual Clock Comparator (DCC)
      6. 7.4.6Disabling N2HET Outputs
      7. 7.4.7High-End Timer Transfer Unit (HTU)
        2. Connections
    5. 7.5 FlexRay Interface
      1. 7.5.1Features
      2. 7.5.2Electrical and Timing Specifications
      3. 7.5.3FlexRay Transfer Unit
    6. 7.6 Controller Area Network (DCAN)
      1. 7.6.1Features
      2. 7.6.2Electrical and Timing Specifications
    7. 7.7 Local Interconnect Network Interface (LIN)
      1. 7.7.1LIN Features
    8. 7.8 Serial Communication Interface (SCI)
      1. 7.8.1Features
    9. 7.9 Inter-Integrated Circuit (I2C)
      1. 7.9.1Features
      2. 7.9.2I2C I/O Timing Specifications
    10. 7.10Multibuffered / Standard Serial Peripheral Interface
      1. 7.10.1Features
      2. 7.10.2MibSPI Transmit and Receive RAM Organization
      3. 7.10.3MibSPI Transmit Trigger Events
        1. Event Trigger Hookup
        2. Event Trigger Hookup
        3. Event Trigger Hookup
      4. 7.10.4MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.10.5SPI Slave Mode I/O Timings
  8. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1Development Support
      2. 8.1.2Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1Related Documentation from Texas Instruments
    3. 8.3 Related Links
    4. 8.4 Community Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
    8. 8.8 Device Identification Code Register
    9. 8.9 Die Identification Registers
    10. 8.10Module Certifications
      1. 8.10.1FlexRay™ Certifications
      2. 8.10.2DCAN Certification
      3. 8.10.3LIN Certification
        1. Master Mode
        2. Slave Mode - Fixed Baud Rate
        3. Slave Mode - Adaptive Baud Rate
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZWT|337
  • PGE|144
Orderable Information

1 Device Overview

1.1 Features

  • High-Performance Automotive-Grade Microcontroller for Safety-Critical Applications
    • Dual CPUs Running in Lockstep
    • ECC on Flash and RAM Interfaces
    • Built-In Self-Test (BIST) for CPU and On-chip RAMs
    • Error Signaling Module With Error Pin
    • Voltage and Clock Monitoring
  • ARM®Cortex®-R4F 32-Bit RISC CPU
    • Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline
    • FPU With Single- and Double-Precision
    • 12-Region Memory Protection Unit (MPU)
    • Open Architecture With Third-Party Support
  • Operating Conditions
    • System Clock up to 180 MHz
    • Core Supply Voltage (VCC): 1.2 V Nominal
    • I/O Supply Voltage (VCCIO): 3.3 V Nominal
    • ADC Supply Voltage (VCCAD): 3.0 to 5.25 V
  • Integrated Memory
    • 3MB of Program Flash With ECC (LS3135)
    • 2MB of Program Flash With ECC (LS2135/2125)
    • 256KB of RAM With ECC (LS3135/2135)
    • 192KB of RAM With ECC (LS2125)
    • 64KB of Flash With ECC for Emulated EEPROM
  • 16-Bit External Memory Interface
  • Common Platform Architecture
    • Consistent Memory Map Across Family
    • Real-Time Interrupt (RTI) Timer OS Timer
    • 96-Channel Vectored Interrupt Module (VIM)
    • 2-Channel Cyclic Redundancy Checker (CRC)
  • Direct Memory Access (DMA) Controller
    • 16 Channels and 32 Control Packets
    • Parity Protection for Control Packet RAM
    • DMA Accesses Protected by Dedicated MPU
  • Frequency-Modulated Phase-Locked Loop (FMPLL) With Built-In Slip Detector
  • Separate Nonmodulating PLL for FlexRay™
  • Trace and Calibration Capabilities
    • Embedded Trace Macrocell (ETM-R4)
    • Data Modification Module (DMM)
    • RAM Trace Port (RTP)
    • Parameter Overlay Module (POM)
  • Multiple Communication Interfaces
    • FlexRay Controller With Two Channels
      • 8KB of Message RAM With Parity Protection
      • Dedicated Transfer Unit (FTU)
    • Three CAN Controllers (DCANs)
      • 64 Mailboxes, Each With Parity Protection
      • Compliant to CAN Protocol Version 2.0B
    • Standard Serial Communication Interface (SCI)
    • Local Interconnect Network (LIN) Interface Controller
      • Compliant to LIN Protocol Version 2.1
      • Can be Configured as a Second SCI
    • Inter-Integrated Circuit (I2C)
    • Three Multibuffered Serial Peripheral Interfaces (MibSPIs)
      • 128 Words With Parity Protection Each
    • Two Standard Serial Peripheral Interfaces (SPIs)
  • Two Next Generation High-End Timer (N2HET) Modules
    • N2HET1: 32 Programmable Channels
    • N2HET2: 18 Programmable Channels
    • 160-Word Instruction RAM Each With Parity Protection
    • Each N2HET Includes Hardware Angle Generator
    • Dedicated High-End Transfer Unit (HTU) With MPU for Each N2HET
  • Two 12-Bit Multibuffered ADC Modules
    • ADC1: 24 Channels
    • ADC2: 16 Channels Shared With ADC1
    • 64 Result Buffers With Parity Protection Each
  • General-Purpose Input/Output (GPIO) Pins Capable of Generating Interrupts
    • Sixteen Pins on the ZWT Package
    • Four Pins on the PGE Package
  • IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight™ Components
  • JTAG Security Module
  • Packages
    • 144-Pin Quad Flatpack (PGE) [Green]
    • 337-Ball Grid Array (ZWT) [Green]

1.2 Applications

  • Braking Systems (Antilock Brake Systems and Electronic Stability Control)
  • Electric Power Steering
  • HEV and EV Inverter Systems
  • Battery Management Systems
  • Active Driver Assistance Systems
  • Aerospace and Avionics
  • Railway Communications
  • Off-road Vehicles

1.3 Description

The TMS570LS31x5/21x5 device is a high-performance automotive-grade microcontroller family for safety systems. The safety architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC on both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os.

The TMS570LS31x5/21x5 device integrates the ARM Cortex-R4F Floating-Point CPU. The CPU offers an efficient 1.66 DMIPS/MHz, and has configurations that can run up to 180 MHz, providing up to 298 DMIPS. The device supports the word-invariant big-endian [BE32] format.

The TMS570LS3135 device has 3MB of integrated flash and 256KB of data RAM. The TMS570LS2135 device has 2MB of integrated flash and 256KB of data RAM. The TMS570LS2125 device has 2MB of integrated flash and 192KB of data RAM. Both the flash and RAM have single-bit error correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable, and programmable memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as I/O supply) for all read, program, and erase operations. When in pipeline mode, the flash operates with a system clock frequency of up to 180 MHz. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and double-word modes.

The TMS570LS31x5/21x5 device features peripherals for real-time control-based applications, including two Next Generation High-End Timer (N2HET) timing coprocessors and two 12-bit Analog-to-Digital Converters (ADCs) supporting up to 24 inputs.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs, capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU.

The device has two 12-bit-resolution MibADCs with 24 channels and 64 words of parity-protected buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are three separate groupings. Each sequence can be converted once when triggered or configured for continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with older devices or faster conversion time is desired.

The device has multiple communication interfaces: three MibSPIs, two SPIs, one LIN, one SCI, three DCANs, one I2C module, and one FlexRay controller. The SPIs provide a convenient method of serial high-speed communication between similar shift-register type devices. The LIN supports the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format.

The DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for systems operating in noisy and harsh environments (for example, automotive vehicle networking and industrial fieldbus) that require reliable serial communication or multiplexed wiring.

The FlexRay controller uses a dual-channel serial, fixed time base multimaster communication protocol with communication rates of 10 Mbps per channel. A FlexRay Transfer Unit (FTU) enables autonomous transfers of FlexRay data to and from the CPU main memory. Transfers are protected by a dedicated, built-in MPU.

The I2C module is a multimaster communication module providing an interface between the microcontroller and an I2C-compatible device through the I2C serial bus. The I2C supports speeds of 100 and 400 Kbps.

The Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external frequency reference to a higher frequency for internal use. There are two FMPLL modules on this device. These modules, when enabled, provide two of the seven possible clock source inputs to the Global Clock Module (GCM). The GCM manages the mapping between the available clock sources and the device clock domains.

The device also has an External Clock Prescaler (ECP) module that when enabled, outputs a continuous external clock on the ECLK pin (or ball). The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of the device operating frequency.

The DMA controller has 16 channels, 32 control packets, and parity protection on its memory. An MPU is built into the DMA to limit the DMA to prescribed areas of memory and to protect the rest of the memory system from any malfunction of the DMA.

The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt is generated or the external ERROR pin is toggled when a fault is detected. The ERROR pin can be monitored externally as an indicator of a fault condition in the microcontroller.

The External Memory Interface (EMIF) provides off-chip expansion capability with the ability to interface to synchronous DRAM (SDRAM) devices, asynchronous memories, peripherals or FPGA devices.

Several interfaces are implemented to enhance the debugging capabilities of application code. In addition to the built-in ARM Cortex-R4F CoreSight debug features, an External Trace Macrocell (ETM) provides instruction and data trace of program execution. For instrumentation purposes, a RAM Trace Port (RTP) module is implemented to support high-speed tracing of RAM and peripheral accesses by the CPU or any other master. A Data Modification Module (DMM) gives the ability to write external data into the device memory. Both the RTP and DMM have no or only minimum impact on the program execution time of the application code. A Parameter Overlay Module (POM) can reroute flash accesses to internal memory or to the EMIF. This rerouting allows the dynamic calibration against production code of parameters and tables without rebuilding the code to explicitly access RAM or halting the processor to reprogram the data flash.

With integrated safety features and a wide choice of communication and control peripherals, the TMS570LS31x5/21x5 device is an ideal solution for high-performance real-time control applications with safety-critical requirements.

Device Information(1)

TMS570LS2125ZWTNFBGA (337)16.0 mm × 16.0 mm
TMS570LS2125PGELQFP (144) 20.0 mm × 20.0 mm
TMS570LS2135ZWTNFBGA (337)16.0 mm × 16.0 mm
TMS570LS2135PGELQFP (144) 20.0 mm × 20.0 mm
TMS570LS3135ZWTNFBGA (337)16.0 mm × 16.0 mm
TMS570LS3135PGELQFP (144) 20.0 mm × 20.0 mm
(1) For more information, see Section 9, Mechanical Packaging and Orderable Information.

1.4 Functional Block Diagram

TMS570LS3135 TMS570LS2135 TMS570LS2125 fbd_f3_MP_pns160.gif
A. For devices with 192KB RAM with ECC, the RAM #3 power domain is not supported.
B. The TMS570LS2135 and TMS570LS2125 devices only support 2MB of Flash with ECC.
Figure 1-1 Functional Block Diagram