SLIS135E December   2010  – February 2017

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Operating Characteristics
    7. 6.7 SPI Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Dual Channel, 256-Position Resolution
      2. 7.3.2 Non-Volatile Memory
    4. 7.4 Device Functional Modes
      1. 7.4.1 Voltage Divider Mode
      2. 7.4.2 Rheostat Mode
      3. 7.4.3 Ideal Resistance Values
    5. 7.5 Programming
      1. 7.5.1 SPI Digital Interface
    6. 7.6 Register Map
      1. 7.6.1 Digital Interface Format
      2. 7.6.2 Write-Wiper Register (Command 00)
      3. 7.6.3 Write-NV Register (Command 01)
      4. 7.6.4 Copy Wiper Register to NV Register (Command 10)
      5. 7.6.5 Copy NV Register to Wiper Register (Command 11)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power Sequence
    2. 9.2 Wiper Position Upon Power Up
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

Many applications require using a digital potentiometer such as the TPL0202 for variable resistance or voltage division; the following application shows a few examples. In conjunction with various amplifiers, the TPL0202 can effectively be used in rheostat mode to modify the gain of an amplifier, in voltage divider mode to create a digital-to-analog converter (DAC), or one of the potentiometers can be used in voltage divider mode while the other is in rheostat mode to create a variable current sink.

Digital potentiometers have additional use cases. See the Related Documentation section for additional resources that have application examples including adjustable current source and gain adjustment.

8.2 Typical Application

The following typical application shows a DAC.

TPL0202 apps_dac_slis135.gif Figure 28. DAC Schematic

8.2.1 Design Requirements

Table 3 shows the design parameters for this application.

Table 3. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 0 to 5 V
Output voltage range 0 to 5 V

8.2.2 Detailed Design Procedure

The TPL0202 can be used in voltage divider mode with a unity-gain operational amplifier buffer to create an 8-bit DAC. The analog output voltage of the circuit is determined by the wiper setting programmed through the I2C bus.

The operational amplifier is required to buffer the high-impedance output of the TPL0202 or else loading placed on the output of the voltage divider will affect the output voltage.

8.2.3 Application Curve

The voltage at terminal H determines the maximum analog voltage at the output. As the TPL0202 moves from zero-scale to full-scale, the voltage divider adjusts with relation to the voltage divider formula (Equation 1), resulting in the desired voltage at terminal W. The voltage at terminal W will range linearly from 0 V to the terminal H voltage. In this example, Vin at terminal H is 5 V and 2.7 V.

TPL0202 D001_SLIS135.gif Figure 29. TPL0202 Digital Input vs OPA320 Analog Output (DAC)