SLVSE11A May 2017  – May 2017 TPS2547


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6Electrical Characteristics: High-Bandwidth Switch
    7. 6.7Electrical Characteristics: Charging Controller
    8. 6.8Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1 Standard Downstream Port (SDP) USB 2.0/USB 3.0
      2. 8.3.2 Charging Downstream Port (CDP)
      3. 8.3.3 Dedicated Charging Port (DCP)
        1. BC1.2 and YD/T 1591-2009
        2. Divider Charging Scheme
        3. 1.2-V Charging Scheme
      4. 8.3.4 Wake on USB Feature (Mouse/Keyboard Wake Feature)
        1. 2.0 Background Information
        2. On USB
        3. Slow-Speed and Full-Speed Device Recognition
          1. CTL Pin Timing Requirement After Wake Event and Transition from S3 to S0
      5. 8.3.5 Load Detect
      6. 8.3.6 Power Wake
        1. Power Wake in Notebook System
      7. 8.3.7 Port Power Management (PPM)
        1. of PPM
        2. Details
        3. PPM in a System with Two Charging Ports
      8. 8.3.8 Overcurrent Protection
      9. 8.3.9 FAULT Response
      10. 8.3.10Undervoltage Lockout (UVLO)
      11. 8.3.11Thermal Sense
    4. 8.4Device Functional Modes
      1. 8.4.1DCP Auto Mode
      2. 8.4.2DCP Forced Shorted / DCP Forced Divider1
      3. 8.4.3High-Bandwidth Data Line Switch
      4. 8.4.4Device Truth Table (TT)
  9. Application and Implementation
    1. 9.1Application Information
      1. 9.1.1Output Discharge
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
      2. 9.2.2Detailed Design Procedure
        1. Settings
      3. 9.2.3Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  12. 12Device and Documentation Support
    1. 12.1Documentation Support
      1. 12.1.1Related Documentation
    2. 12.2Receiving Notification of Documentation Updates
    3. 12.3Community Resources
    4. 12.4Trademarks
    5. 12.5Electrostatic Discharge Caution
    6. 12.6Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Orderable Information

Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers must validate and test their design implementation to confirm system functionality.

Application Information

Power-on-reset (POR) holds device in initial state while output is held in discharge mode. Any POR event returns the device to initial state. After POR clears, device goes to the next state depending on the CTL lines as shown in Figure 38.

TPS2547 Fig33_Charging_States_SLVSBJ2.gif Figure 38. TPS2547 Charging States

Output Discharge

To allow a charging port to renegotiate current with a portable device, the TPS2547 device uses the OUT discharge function. The device proceeds by turning off the power switch while discharging OUT. The device then turns on the power switch again to reassert the OUT voltage. This discharge function is automatically applied, as shown in Figure 26. There are two discharge times, tDCHG_L and tDCHG_S. tDCHG_L is from SDP1/SDP2/CDP to DCP_Auto, and tDCHG_S is from DCP_Auto to SDP1/SDP2/CDP.

Typical Application

TPS2547 typ_app_FP_SLVSE11.gif Figure 39. Typical Application Schematic USB Port Charging

Design Requirements

For this design example, use the parameters listed in Table 4.

Table 4. Design Parameters

Input voltage, V(IN)5 V
Output voltage, V(DC)5 V
Maximum continuous output current, I(OUT)2.5 A
Current limit, I(LIM_LO) at RILIM_LO = 80.6 kΩ0.625 A
Current Limit, I(LIM_HI) at RILIM_HI = 16.9 kΩ2.97 A

Detailed Design Procedure

Current-Limit Settings

The TPS2547 has two independent current limit settings that are each programmed externally with a resistor. The ILIM_HI setting is programmed with RILIM_HI connected between ILIM_HI and GND. The ILIM_LO setting is programmed with RILIM_LO connected between ILIM_LO and GND. Consult the Device Truth Table (Table 3) to see when each current limit is used. Both settings have the same relation between the current limit and the programming resistor.

RILIM_LO is optional and the ILIM_LO pin may be left unconnected if the following conditions are met:

  1. ILIM_SEL is always set high
  2. Load Detection - Port Power Management is not used

Equation 1 programs the typical current limit:

Equation 1. TPS2547 EQ1_lvse11.gif

RILIM_XX corresponds to either RILIM_HI or RILIM_LO as appropriate.

TPS2547 App_G1_slvse11.gif
Full RILIM_XX Range
Figure 40. Typical Current Limit Setting vs Programming Resistor

Many applications require that the current limit meet specific tolerance limits. When designing to these tolerance limits, both the tolerance of the TPS2547 current limit and the tolerance of the external programming resistor must be taken into account. The following equations approximate the TPS2547 minimum and maximum current limits to within a few mA, and are appropriate for design purposes. The equations do not constitute part of Texas Instrument's published device specifications for purposes of Texas Instrument's product warranty. These equations assume an ideal - no variation - external programming resistor. To take resistor tolerance into account, first determine the minimum and maximum resistor values based on its tolerance specifications, and use these values in the equations. Because of the inverse relation between the current limit and the programming resistor, use the maximum resistor value in the Equation 2 and the minimum resistor value in the Equation 3.

Equation 2. TPS2547 EQ2_lvse11.gif
Equation 3. TPS2547 EQ3_lvse11.gif
TPS2547 App_G2_slvse11.gif Figure 41. Current Limit Setting vs Programming Resistor
TPS2547 App_G3_slvse11.gif Figure 42. Current Limit Setting vs Programming Resistor

The traces routing the RILIM_XX resistors must be a sufficiently low resistance as to not affect the current-limit accuracy. The ground connection for the RILIM_XX resistors is also very important. The resistors need to reference back to the TPS2547 GND pin. Follow normal board layout practices to ensure that current flow from other parts of the board does not impact the ground potential between the resistors and the TPS2547 GND pin.

Application Curves

TPS2547 ilim_hi_waveform.gif Figure 43. High-Current Limit
TPS2547 iPhone5s_with_TPS2456_label.gif
Figure 45. Charging iPhone 5s with TPS2547
CDP (CTL1 = CTL2 = CTL3 = ILIM_SEL = 1)
TPS2547 ilim_lo_waveform.gif Figure 44. Low-Current Limit