SLVSE11A May 2017  – May 2017 TPS2547

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6Electrical Characteristics: High-Bandwidth Switch
    7. 6.7Electrical Characteristics: Charging Controller
    8. 6.8Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1 Standard Downstream Port (SDP) USB 2.0/USB 3.0
      2. 8.3.2 Charging Downstream Port (CDP)
      3. 8.3.3 Dedicated Charging Port (DCP)
        1. 8.3.3.1DCP BC1.2 and YD/T 1591-2009
        2. 8.3.3.2DCP Divider Charging Scheme
        3. 8.3.3.3DCP 1.2-V Charging Scheme
      4. 8.3.4 Wake on USB Feature (Mouse/Keyboard Wake Feature)
        1. 8.3.4.1USB 2.0 Background Information
        2. 8.3.4.2Wake On USB
        3. 8.3.4.3USB Slow-Speed and Full-Speed Device Recognition
          1. 8.3.4.3.1No CTL Pin Timing Requirement After Wake Event and Transition from S3 to S0
      5. 8.3.5 Load Detect
      6. 8.3.6 Power Wake
        1. 8.3.6.1Implementing Power Wake in Notebook System
      7. 8.3.7 Port Power Management (PPM)
        1. 8.3.7.1Benefits of PPM
        2. 8.3.7.2PPM Details
        3. 8.3.7.3Implementing PPM in a System with Two Charging Ports
      8. 8.3.8 Overcurrent Protection
      9. 8.3.9 FAULT Response
      10. 8.3.10Undervoltage Lockout (UVLO)
      11. 8.3.11Thermal Sense
    4. 8.4Device Functional Modes
      1. 8.4.1DCP Auto Mode
      2. 8.4.2DCP Forced Shorted / DCP Forced Divider1
      3. 8.4.3High-Bandwidth Data Line Switch
      4. 8.4.4Device Truth Table (TT)
  9. Application and Implementation
    1. 9.1Application Information
      1. 9.1.1Output Discharge
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
      2. 9.2.2Detailed Design Procedure
        1. 9.2.2.1Current-Limit Settings
      3. 9.2.3Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  12. 12Device and Documentation Support
    1. 12.1Documentation Support
      1. 12.1.1Related Documentation
    2. 12.2Receiving Notification of Documentation Updates
    3. 12.3Community Resources
    4. 12.4Trademarks
    5. 12.5Electrostatic Discharge Caution
    6. 12.6Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Detailed Description

Overview

The following overview references various industry standards. TI recommends consulting the most up-to-date standard to ensure the most recent and accurate information. Rechargeable portable equipment requires an external power source to charge its batteries. USB ports are a convenient location for charging, because of an available 5-V power source. Universally accepted standards are required to make sure host and client-side devices operate together in a system to ensure power management requirements are met. Traditionally, host ports following the USB 2.0 specification must provide at least 500 mA to downstream client-side devices. Because multiple USB devices can attach to a single USB port through a bus-powered hub, it is the responsibility of the client-side device to negotiate its power allotment from the host, ensuring the total current draw does not exceed 500 mA. In general, each USB device is granted 100 mA, and may request more current in 100-mA unit steps up to 500 mA. The host may grant or deny based on the available current. A USB 3.0 host port not only provides higher data rate than USB 2.0 port, but also raises the unit load from 100 mA to 150 mA. It is also required to provide a minimum current of 900 mA to downstream client-side devices.

Additionally, the success of USB makes the mini-USB connector a popular choice for wall adapter cables. This allows a portable device to charge from both a wall adapter, and USB port with only one connector. As USB charging has gained popularity, the 500-mA minimum defined by USB 2.0 or 900 mA for USB 3.0 has become insufficient for many handset and personal media players, which need a higher charging rate. Wall adapters can provide much more current than 500 mA/900 mA. Several new standards have been introduced, defining protocol handshaking methods that allow host and client devices to acknowledge and draw additional current beyond the 500 mA/900 mA minimum defined by USB 2.0 and 3.0, while still using a single micro-USB input connector.

The TPS2547 supports four of the most common USB charging schemes found in popular handheld media and cellular devices:

  • USB Battery Charging Specification BC1.2
  • Chinese Telecommunications Industry Standard YD/T 1591-2009
  • Divider Mode
  • 1.2-V Mode

YD/T 1591-2009 is a subset of BC1.2 specifications supported by vast majority of devices that implement USB changing. Divider and 1.2-V charging schemes are supported in devices from specific, yet popular device makers.

BC1.2 lists three different port types:

  • Standard Downstream Port (SDP)
  • Charging Downstream Port (CDP)
  • Dedicated Charging Port (DCP)

BC1.2 defines a charging port as a downstream facing USB port that provides power for charging portable equipment. Under this definition, CDP and DCP are defined as charging ports.

Functional Block Diagram

TPS2547 top_level_fbd_SLVSBJ2.gif

Feature Description

Standard Downstream Port (SDP) USB 2.0/USB 3.0

An SDP is a traditional USB port that follows USB 2.0 and 3.0 protocol, and supplies a minimum of 500 mA for USB 2.0 and 900 mA for USB 3.0 per port. USB 2.0 and 3.0 communications is supported, and the host controller must be active to allow charging. TPS2547 supports SDP mode in system power state S0, when system is completely powered ON, and fully operational. For more details on control pin (CTL1-CTL3) settings to program this state, see Table 3.

Charging Downstream Port (CDP)

A CDP is a USB port that follows USB BC1.2 and supplies a minimum of 1.5 A per port. It provides power and meets USB 2.0 requirements for device enumeration. USB 2.0 communications is supported, and the host controller must be active to allow charging. What separates a CDP from an SDP is the host-charge handshaking logic that identifies this port as a CDP. A CDP is identifiable by a compliant BC1.2 client device, and allows for additional current draw by the client device.

The CDP process is done in two steps. During step one, the portable equipment outputs a nominal 0.6-V output on the D+ line, and reads the voltage input on the D– line. The portable device detects it is connected to an SDP if the D– voltage is less than the nominal data detect voltage of 0.3 V. The portable device detects that it is connected to a Charging Port if the D– voltage is greater than the nominal data detect voltage of 0.3 V, and optionally less than 0.8 V.

The second step is necessary for portable equipment to determine if it is connected to CDP or DCP. The portable device outputs a nominal 0.6 V output on its D– line, and reads the voltage input on its D+ line. The portable device detects it is connected to a CDP if the data line being read remains less than the nominal data detect voltage of 0.3 V. The portable device detects it is connected to a DCP if the data line being read is greater than the nominal data detect voltage of 0.3 V.

TPS2547 supports CDP mode in system power state S0 when system is completely powered ON, and fully operational. For more details on control pin (CTL1-CTL3) settings to program this state, see Table 3.

Dedicated Charging Port (DCP)

A DCP only provides power but does not support data connection to an upstream port. As shown in following sections, a DCP is identified by the electrical characteristics of the data lines. The TPS2547 emulates DCP in two charging states, namely DCP Forced and DCP Auto as shown in Figure 37. In DCP Forced state the device supports one of the two DCP charging schemes, namely Divider1 or Shorted. In the DCP Auto state, the device charge detection state machine is activated to selectively implement charging schemes involved with the Shorted, Divider1, Divider2, and 1.2-V modes. Shorted DCP mode complies with BC1.2 and Chinese Telecommunications Industry Standard YD/T 1591-2009, while the Divider and 1.2-V modes are employed to charge devices that do not comply with BC1.2 DCP standard.

DCP BC1.2 and YD/T 1591-2009

Both standards define that the D+ and D– data lines must be shorted together with a maximum series impedance of 200 Ω. This is shown in Figure 28.

TPS2547 Fig28_Shorted_Mode_BC_1_2_DCP_slvse.gif Figure 28. DCP Supporting BC1.2/YD/T 1591-2009

DCP Divider Charging Scheme

There are two Divider charging scheme supported by the device, Divider1 and Divider2 as shown in Figure 29 and Figure 30. In Divider1 charging scheme the device applies 2 V and 2.7 V to D+ and D– data line respectively. This is reversed in Divider2 mode.

TPS2547 Fig29_Divider1_Mode_SLVSE11.gif Figure 29. DCP Divider1 Charging Scheme
TPS2547 Fig30_Divider2_Mode_SLVSE11.gif Figure 30. Divider2 Charging Scheme

DCP 1.2-V Charging Scheme

1.2-V charging scheme is used by some handheld devices to enable fast charging at 2 A. TPS2547 supports this scheme in the DCP-Auto mode before the device enters BC1.2 shorted mode. To simulate this charging scheme D+/D– lines are shorted and pulled-up to 1.2 V for fixed duration then device moves to DCP shorted mode as defined in BC1.2 specification. This is shown in Figure 31.

TPS2547 Fig31_1_2_2V_Mode_SLVSE11.gif Figure 31. DCP 1.2-V Charging Scheme

Wake on USB Feature (Mouse/Keyboard Wake Feature)

USB 2.0 Background Information

The TPS2547 data lines interface with USB 2.0 devices. USB 2.0 defines three types of devices according to data rate. These devices and their characteristics relevant to TPS2547 Wake on USB operation are shown below.

Low-speed USB devices:

  • 1.5 Mbps
  • Wired mice and keyboards are examples
  • No devices that need battery charging
  • All signaling performed at 2 V and 0.8 V hi/lo logic levels
  • D– high to signal connect and when placed into suspend
  • D– high when not transmitting data packets

Full-speed USB devices:

  • 12 Mbps
  • Wireless mice and keyboards are examples
  • Legacy phones and music players are examples
  • Some legacy devices that need battery charging
  • All signaling performed at 2 V and 0.8 V hi/lo logic levels
  • D+ high to signal connect and when placed into suspend
  • D+ high when not transmitting data packets

High-speed USB devices:

  • 480 Mbps
  • Tablets, phones and music players are examples
  • Many devices that need battery charging
  • Connect and suspend signaling performed at 2 V and 0.8 V hi/lo logic levels
  • Data packet signaling performed a logic levels below 0.8 V
  • D+ high to signal connect and when placed into suspend (same as a full-speed device)
  • D+ and D– low when not transmitting data packets

Wake On USB

Wake on USB is the ability of a wake configured USB device to wake a computer system from its S3 sleep state back to its S0 working state. Wake on USB requires the data lines to be connected to the system USB host before the system is placed into its S3 sleep state, and remain continuously connected until they are used to wake the system.

The TPS2547 supports low-speed and high-speed HID (human interface device like mouse/key board) wake function. There are two scenarios under which wake on mouse are supported by the TPS2547. The specific CTL pin changes that the TPS2547 overrides are shown below. The information is presented as CTL1, CTL2, CTL3. The ILIM_SEL pin plays no role.

  1. 111 (CDP/SDP2) to 011 (DCP-Auto)
  2. 010 (SDP1) to 011 (DCP-Auto)

NOTE

The 110 (SDP1) to 011 (DCP-Auto) transition is not supported. This is done for practical reasons, because the transition involves changes to two CTL pins. Depending on which CTL pin changes first, the device sees either a temporary 111 or 010 command. The 010 command is safe but the 111 command causes an OUT discharge as the TPS2547 instead proceeds to the 111 state.

USB Slow-Speed and Full-Speed Device Recognition

TPS2547 is capable of detecting LS or FS device attachment when TPS2547 is in SDP or CDP mode. Per USB specification, when no device is attached, the D+ and D– lines are near ground level. When a low-speed compliant device is attached to the TPS2547 charging port, D– line is pulled high in its idle state (mouse/keyboard not activated). However, when a FS device is attached then the opposite is true in its idle state, that is, D+ is pulled high and D– remains at ground level.

TPS2547 monitors both D+ and D– lines while CTL pin settings are in CDP or SDP mode to detect LS or FS HID device attachment. To support HID sleep wake, TPS2547 must first determine that it is attached to a LS or FS device when system is in S0 power state. TPS2547 does this as described above. While supporting a LS HID wake is straight forward, supporting FS HID requires making a distinction between a FS and a HS device. This is because a high-speed device always presents itself initially as a full speed device (by a 1.5-K pullup resistor on D+). The negotiation for high speed then makes the distinction whereby the 1.5-K pullup resistor gets removed.

TPS2547 handles the distinction between a FS and HS device at connect by memorizing if the D+ line goes low after connect. A HS device after connect always undergoes negotiation for HS, which requires the 1.5-kΩ resistor pullup on D+ to be removed. To memorize a FS device, TPS2547 requires the device to remain connected for at least 60 seconds while the system is in S0 mode, before placing it in sleep or S3 mode.

NOTE

If system is placed in sleep mode earlier than the 60 second window, a FS device may not get recognized and hence could fail to wake system from S3. This requirement does not apply for LS device.

No CTL Pin Timing Requirement After Wake Event and Transition from S3 to S0

Unlike the TPS2543, there is no CTL pin timing requirement for the TPS2547 when the wake configured USB device wakes the system from S3 back to S0. The TPS2543 requires the CTL pins to transition from the DCP-Auto setting back to the SDP/CDP setting within 64 ms of the attached USB device signaling a wake event (for example, mouse clicked or keyboard key pressed). No such timing condition exists for the TPS2547.

Load Detect

TPS2547 offers system designers unique power management strategy not available in the industry from similar devices. There are two power management schemes supported by the TPS2547 through the STATUS pin, they are:

  • Power Wake (PW)
  • Port Power Management (PPM)

Either feature may be implemented in a system depending on power savings goals for the system. In general, Power Wake feature is used mainly in mobile systems, like a notebook, where it is imperative to save battery power when system is in deep sleep (S4/S5) state. Oppositely, Port Power Management feature would be implemented where multiple charging ports are supported in the same system, and system power rating is not capable of supporting high-current charging on multiple ports simultaneously.

Power Wake

The goal of the power wake feature is to save system power when the system is in S4/S5 state. In the S4/S5 state, the system is in deep sleep and typically running off the battery; so every mW in system power savings translates to extending battery life. In this state, the TPS2547 monitors charging current at the OUT pin and provide a mechanism through the STATUS pin to switch out the high-power DC-DC controller and switch in a low power LDO when charging current requirement is < 45 mA (typical). This would be the case when no peripheral device is connected at the charging port or if a device has attained its full battery charge and draws <45 mA. A power wake flow chart and description is shown in Figure 32.

TPS2547 Fig34_mouse_wake_SLVSE11.gif Figure 32. Power Wake Flow Chart

Implementing Power Wake in Notebook System

An implementation of power wake in notebook platforms with the TPS2547 is shown in Figure 33 to Figure 35. Power wake function is used to select between a high-power DC-DC converter, and low-power LDO (100 mA) based on charging requirements. System power saving is achieved when under no charging conditions (the connected device is fully charged or no device is connected) the DC-DC converter is turned off (to save power because it is less efficient in low-power operating region) and the low-power LDO supplies standby power to the charging port.

Power wake is activated in S4/S5 mode (0011 setting, see Table 3), TPS2547 is charging connected device as shown in Figure 33, STATUS is pulled LO (Case 1) which switches-out the LDO and switches-in the DC-DC converter to handle high-current charging.

TPS2547 Fig35_PW_Flow_Chart_SLVSE11.gif Figure 33. Case 1: System in S4/S5, Device Charging

As shown in Figure 34 and Figure 35, when connected device is fully charged or gets disconnected from the charging port, the charging current falls. If charging current falls to < 45 mA and stays below this threshold for over 15 s, TPS2547 automatically sets a 55-mA internal current limit and STATUS is de-asserted (pulled HI). As shown in Figure 34 and Figure 35. This results in DC-DC converter turning off, and the LDO turning on. Current limit of 55 mA is set to prevent the low-power LDO output voltage from collapsing in case there is a spike in current draw due to device attachment or other activity such as display panel LED turning ON in connected device.

Following Power Wake flow chart (Figure 32) when a device is attached and draws > 55 mA of charging current the TPS2547 hits its internal current limit. This triggers the device to assert STATUS (LO), and turn on the DC-DC converter and turn off the LDO. TPS2547 discharges OUT for > 2 s (typical), allowing the main power supply to turn on. After the discharge, the device turns back on with current limit set by ILIM_HI (Case 1).

TPS2547 case_2A_slvse11.gif Figure 34. Case 2A: System in S4/S5, No Device Attached
TPS2547 Fig37_Power_Wake_CASE2_SLVSE11.gif Figure 35. Case 2B: System in S4/S5, Attached Device Fully Charged

Port Power Management (PPM)

PPM is the intelligent and dynamic allocation of power for systems that have multiple charging ports but cannot power them all simultaneously. The goals of this feature are:

  • Enhance user experience because user does not have to search for charging port
  • Ensure the power supply only has to be designed for a reasonable charging load

Initially all ports are allowed to broadcast high-current charging, charging current limit is based on ILIM_HI resistor setting. System monitors STATUS to see when high-current loads are present. Once allowed number of ports assert STATUS, remaining ports are toggled to a non-charging port. Non-charging ports are SDP ports with current limit based on ILIM_LO. TPS2547 allows for a system to toggle between charging and non-charging ports either with an OUT discharge or without an OUT discharge.

Benefits of PPM

  • Delivers better user experience
  • Prevents overloading of system's power supply
  • Allows for dynamic power limits based on system state
  • Allows every port to potentially be a high-power charging port
  • Allows for smaller power supply capacity because the loading is controlled

PPM Details

All ports are allowed to broadcast high-current charging – CDP or DCP. Current limit is based on ILIM_HI and system monitors STATUS pin to see when high-current loads are present. Once allowed number of ports assert STATUS, remaining ports are toggled to a SDP non-charging port. SDP current limit is based on ILIM_LO setting. SDP ports are automatically toggled back to CDP or DCP mode when a charging port de-asserts STATUS.

Based on CTL settings there is a provision for a port to toggle between charging and non-charging ports either with a Vbus discharge or without a Vbus discharge. For example when a port is in SDP2 mode (1110) and its ILIM_SEL pin is toggled to 1 due to another port releasing its high-current requirements. The SDP2 port automatically reverts to CDP mode (1111) without a discharge event. This is desirable if this port was connected to a media device where it was syncing data from the SDP2 port; a discharge event would disrupt the syncing activity on the port and cause user confusion.

STATUS trip point is based on the programmable ILIM_LO current limit set point. This does not mean STATUS is a current limit – the port itself is using the ILIM_HI current limit. Since ILIM_LO defines the current limit for a SDP port, it works well to use the ILIM_LO value to define a high-current load. STATUS asserts in CDP and DCP when load current is above ILIM_LO+60 mA for 200 ms. STATUS also asserts in CDP when an attached device does a BC1.2 primary detection. STATUS de-asserts in CDP and DCP when the load current is below ILIM_LO+10 mA for 3 s.

Implementing PPM in a System with Two Charging Ports

Figure 36 shows implementation of two charging ports, each with its own TPS2547. In this example 5-V power supply for the two charging ports is rated at < 3 A or < 15 W maximum. Both devices have RLIM chosen to correspond to the low (0.9 A) and high (1.5 A) current limit setting for the port. In this implementation the system can support only one of the two ports at 1.5-A charging current while the other port is set to SDP mode and ILIMIT corresponding to 0.9 A.

TPS2547 PPM_slvse11.gif Figure 36. Implementing Port Power Management in a System Supporting Two Charging Ports

Overcurrent Protection

When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Two possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before VIN has been applied. The TPS2547 senses the short and immediately switches into a constant-current output. In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload occurs, high currents may flow for nominally one to two microseconds before the current-limit circuit can react. The device operates in constant-current mode after the current-limit circuit has responded. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting. The device remains off until the junction temperature cools approximately 20°C and then re-starts. The device continues to cycle on/off until the overcurrent condition is removed.

FAULT Response

The FAULT open-drain output is asserted (active low) during an overtemperature or current limit condition. The output remains asserted until the fault condition is removed. The TPS2547 is designed to eliminate false FAULT reporting by using an internal de-glitch circuit for current limit conditions without the need for external circuitry. This ensures that FAULT is not accidentally asserted due to normal operation such as starting into a heavy capacitive load. overtemperature conditions are not de-glitched and assert the FAULT signal immediately.

Undervoltage Lockout (UVLO)

The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO turnon threshold. Built-in hysteresis prevents unwanted oscillations on the output due to input voltage drop from large current surges.

Thermal Sense

The TPS2547 protects itself with two independent thermal sensing circuits that monitor the operating temperature of the power distribution switch and disables operation if the temperature exceeds recommended operating conditions. The device operates in constant-current mode during an overcurrent condition, which increases the voltage drop across power switch. The power dissipation in the package is proportional to the voltage drop across the power switch, so the junction temperature rises during an overcurrent condition. The first thermal sensor turns off the power switch when the die temperature exceeds 135°C and the part is in current limit. The second thermal sensor turns off the power switch when the die temperature exceeds 155°C regardless of whether the power switch is in current limit. Hysteresis is built into both thermal sensors, and the switch turns on after the device has cooled by approximately 20°C. The switch continues to cycle off and on until the fault is removed. The open-drain false reporting output FAULT is asserted (active low) during an overtemperature shutdown condition.

Device Functional Modes

Table 1 shows the differences between these ports.

Table 1. Operating Modes

PORT TYPESUPPORT USB
2.0 COMMUNICATION
MAXIMUM ALLOWABLE CURRENT
DRAW BY PORTABLE DEVICE (A)
SDP (USB 2.0)Yes0.5
SDP (USB 3.0)Yes0.9
CDPYes1.5
DCPNo1.5

DCP Auto Mode

As mentioned above the TPS2547 integrates an auto-detect state machine that supports all the above DCP charging schemes. It starts in Divider1 scheme, however if a BC1.2 or YD/T 1591-2009 compliant device is attached, the TPS2547 responds by discharging OUT, turning back on the power switch and operating in 1.2 V mode briefly and then moving to BC1.2 DCP mode. It then stays in that mode until the device releases the data line, in which case it goes back to Divider1 scheme. When a Divider1 compliant device is attached the TPS2547 stays in Divider1 state.

Also, the TPS2547 automatically switches between the Divider1 and Divider2 schemes based on charging current drawn by the connected device. Initially the device sets the data lines to Divider1 scheme. If charging current of > 750 mA is measured by the TPS2547 it switches to Divider2 scheme and test to see if the peripheral device still charges at a high current. If it does then it stays in Divider2 scheme otherwise it reverts to Divider1 scheme.

TPS2547 Fig32_DCP_Auto_SLVSE11.gif Figure 37. DCP Auto Mode

DCP Forced Shorted / DCP Forced Divider1

In this mode the device is permanently set to one of the DCP schemes (BC1.2/ YD/T 1591-2009 or Divider1) as commanded by its control pin setting per Table 3.

High-Bandwidth Data Line Switch

The TPS2547 passes the D+ and D– data lines through the device to enable monitoring and handshaking while supporting charging operation. A wide bandwidth signal switch is used, allowing data to pass through the device without corrupting signal integrity. The data line switches are turned on in any of CDP or SDP operating modes. The EN input also needs to be at logic High for the data line switches to be enabled.

NOTE

  • While in CDP mode, the data switches are ON even while CDP handshaking is occurring
  • The data line switches are OFF if EN or all CTL pins are held low, or if in DCP mode. They are not automatically turned off if the power switch (IN to OUT) is in current limit
  • The data switches are for USB 2.0 differential pair only. In the case of a USB 3.0 host, the super speed differential pairs must be routed directly to the USB connector without passing through the TPS2547
  • Data switches are OFF during OUT (VBUS) discharge

Table 2 can be used as an aid to program the TPS2547 per system states however not restricted to below settings only.

Table 2. Control Pin Settings Matched to System Power States

SYSTEM GLOBAL
POWER
STATE
TPS2547 CHARGING MODECTL1CTL2CTL3ILIM_SELCURRENT LIMIT
SETTING
S0SDP11101 or 0ILIM_HI / ILIM_LO
S0SDP2, no discharge to / from CDP1110ILIM_LO
S0CDP, load detection with ILIM_LO + 60-mA thresholds or if a BC1.2 primary detection occurs1111ILIM_HI
S4/S5Auto mode, load detection with power wake thresholds0011ILIM_HI
S3/S4/S5Auto mode, no load detection0010ILIM_HI
S3Auto mode, keyboard/mouse wake up, load detection with ILIM_LO + 60 mA thresholds0111ILIM_HI
S3Auto mode, keyboard/mouse wake-up, no load detection0110ILIM_HI
S3SDP1, keyboard/mouse wake-up0101 or 0ILIM_HI / ILIM_LO

Device Truth Table (TT)

Device TT lists all valid bias combinations for the three control pins CTL1-3 and ILIM_SEL pin and their corresponding charging mode. It is important to note that the TT purposely omits matching charging modes of the TPS2547 with global power states (S0-S5) as device is agnostic to system power states. The TPS2547 monitors CTL inputs and transitions to the charging state it is commanded to go to (except when LS/FS HID device is detected). For example, if sleep charging is desired when system is in standby or hibernate state then the user must set TPS2547 CTL pins to correspond to DCP_Auto charging mode as shown in the below table. When the system resumes operation mode set the control pins to correspond to SDP or CDP mode, as seen in Table 3.

Table 3. Truth Table

CTL1CTL2CTL3ILIM_SELMODECURRENT
LIMIT
SETTING
STATUS OUTPUT
(ACTIVE LOW)
COMMENT
0000DischargeNAOFFOUT held low.
0001DischargeNAOFF
0010DCP_AutoILIM_HIOFFData lines disconnected.
0011DCP_AutoIOS_PW & ILIM_HI(1)DCP load present(2)Data lines disconnected and load detect function active.
0100SDP1ILIM_LOOFFData lines connected.
0101SDP1ILIM_HIOFF
0110DCP_AutoILIM_HIOFFData lines disconnected.
0111DCP_AutoILIM_HIDCP load present(3)Data lines disconnected and load detect function active.
1000DCP _ShortedILIM_LOOFFDevice forced to stay in DCP BC1.2 charging mode.
1001DCP_ShortedILIM_HIOFF
1010DCP / Divider1ILIM_LOOFFDevice forced to stay in DCP divider1 charging mode.
1011DCP / Divider1ILIM_HIOFF
1100SDP1ILIM_LOOFFData lines connected.
1101SDP1ILIM_HIOFF
1110SDP2(4)ILIM_LOOFF
1111CDP(4)ILIM_HICDP load present(5)Data lines connected and load detect active.
TPS2547 : Current limit (IOS) is automatically switched between IOS_PW and the value set by ILIM_HI according to the Load Detect – Power Wake functionality.
DCP Load present governed by the Load Detection – Power Wake limits.
DCP Load present governed by the Load Detection – Non Power Wake limits.
No OUT discharge when changing between 1111 and 1110.
CDP Load present governed by the Load Detection – Non Power Wake limits and BC1.2 primary detection.