SLVSE11A May 2017  – May 2017 TPS2547


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6Electrical Characteristics: High-Bandwidth Switch
    7. 6.7Electrical Characteristics: Charging Controller
    8. 6.8Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1 Standard Downstream Port (SDP) USB 2.0/USB 3.0
      2. 8.3.2 Charging Downstream Port (CDP)
      3. 8.3.3 Dedicated Charging Port (DCP)
        1. BC1.2 and YD/T 1591-2009
        2. Divider Charging Scheme
        3. 1.2-V Charging Scheme
      4. 8.3.4 Wake on USB Feature (Mouse/Keyboard Wake Feature)
        1. 2.0 Background Information
        2. On USB
        3. Slow-Speed and Full-Speed Device Recognition
          1. CTL Pin Timing Requirement After Wake Event and Transition from S3 to S0
      5. 8.3.5 Load Detect
      6. 8.3.6 Power Wake
        1. Power Wake in Notebook System
      7. 8.3.7 Port Power Management (PPM)
        1. of PPM
        2. Details
        3. PPM in a System with Two Charging Ports
      8. 8.3.8 Overcurrent Protection
      9. 8.3.9 FAULT Response
      10. 8.3.10Undervoltage Lockout (UVLO)
      11. 8.3.11Thermal Sense
    4. 8.4Device Functional Modes
      1. 8.4.1DCP Auto Mode
      2. 8.4.2DCP Forced Shorted / DCP Forced Divider1
      3. 8.4.3High-Bandwidth Data Line Switch
      4. 8.4.4Device Truth Table (TT)
  9. Application and Implementation
    1. 9.1Application Information
      1. 9.1.1Output Discharge
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
      2. 9.2.2Detailed Design Procedure
        1. Settings
      3. 9.2.3Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  12. 12Device and Documentation Support
    1. 12.1Documentation Support
      1. 12.1.1Related Documentation
    2. 12.2Receiving Notification of Documentation Updates
    3. 12.3Community Resources
    4. 12.4Trademarks
    5. 12.5Electrostatic Discharge Caution
    6. 12.6Glossary
  13. 13Mechanical, Packaging, and Orderable Information


Layout Guidelines

For the trace routing of DP_IN, DM_IN, DP_OUT, and DM_OUT: route these traces as micro-strips with nominal differential impedance of 90 Ω. Minimize the use of vias in the high-speed data lines. Keep the reference GND plane devoid from cuts or splits above the differential pairs to prevent impedance discontinuities. For more information, see the High-Speed USB Platform Design Guidelines from Intel.

The trace routing from the upstream regulator to the TPS2547 IN pin must be as short as possible to reduce voltage drop and parasitic inductance.

In order to meet IEC61000-4-2 level 4 ESD, external circuitry is required. Refer to the guidelines provided in the Related Documentation section.

The traces routing from the RILIM_HI and RILIM_LO resistors to the device must be as short as possible to reduce parasitic effects on the current-limit accuracy.

The thermal pad must be directly connected to the PCB ground plane using wide and short copper trace.

Layout Example

TPS2547 layout_guidelines_tps2546.gif Figure 46. Layout Recommendation