SLVSE11A May 2017  – May 2017 TPS2547

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6Electrical Characteristics: High-Bandwidth Switch
    7. 6.7Electrical Characteristics: Charging Controller
    8. 6.8Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1 Standard Downstream Port (SDP) USB 2.0/USB 3.0
      2. 8.3.2 Charging Downstream Port (CDP)
      3. 8.3.3 Dedicated Charging Port (DCP)
        1. 8.3.3.1DCP BC1.2 and YD/T 1591-2009
        2. 8.3.3.2DCP Divider Charging Scheme
        3. 8.3.3.3DCP 1.2-V Charging Scheme
      4. 8.3.4 Wake on USB Feature (Mouse/Keyboard Wake Feature)
        1. 8.3.4.1USB 2.0 Background Information
        2. 8.3.4.2Wake On USB
        3. 8.3.4.3USB Slow-Speed and Full-Speed Device Recognition
          1. 8.3.4.3.1No CTL Pin Timing Requirement After Wake Event and Transition from S3 to S0
      5. 8.3.5 Load Detect
      6. 8.3.6 Power Wake
        1. 8.3.6.1Implementing Power Wake in Notebook System
      7. 8.3.7 Port Power Management (PPM)
        1. 8.3.7.1Benefits of PPM
        2. 8.3.7.2PPM Details
        3. 8.3.7.3Implementing PPM in a System with Two Charging Ports
      8. 8.3.8 Overcurrent Protection
      9. 8.3.9 FAULT Response
      10. 8.3.10Undervoltage Lockout (UVLO)
      11. 8.3.11Thermal Sense
    4. 8.4Device Functional Modes
      1. 8.4.1DCP Auto Mode
      2. 8.4.2DCP Forced Shorted / DCP Forced Divider1
      3. 8.4.3High-Bandwidth Data Line Switch
      4. 8.4.4Device Truth Table (TT)
  9. Application and Implementation
    1. 9.1Application Information
      1. 9.1.1Output Discharge
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
      2. 9.2.2Detailed Design Procedure
        1. 9.2.2.1Current-Limit Settings
      3. 9.2.3Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  12. 12Device and Documentation Support
    1. 12.1Documentation Support
      1. 12.1.1Related Documentation
    2. 12.2Receiving Notification of Documentation Updates
    3. 12.3Community Resources
    4. 12.4Trademarks
    5. 12.5Electrostatic Discharge Caution
    6. 12.6Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Specifications

Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)
MINMAXUNIT
VoltageIN, EN, ILIM_LO, ILIM_HI, FAULT, STATUS, ILIM_SEL, CTL1, CTL2, CTL3, OUT–0.37 V
IN to OUT–77
DP_IN, DM_IN, DP_OUT, DM_OUT–0.3(IN + 0.3) or 5.7
Input clamp currentDP_IN, DM_IN, DP_OUT, DM_OUT±20mA
Continuous current in SDP or CDP modeDP_IN to DP_OUT or DM_IN to DM_OUT±100mA
Continuous current in BC1.2 DCP modeDP_IN to DM_IN±50mA
Continuous output currentOUTInternally limited
Continuous output sink currentFAULT, STATUS25mA
Continuous output source currentILIM_LO, ILIM_HIInternally limitedmA
Operating junction temperature, TJ–40Internally limited°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)HBM±2000V
HBM wrt GND and each other, DP_IN, DM_IN, OUT±8000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

voltages are referenced to GND (unless otherwise noted)
MINMAXUNIT
VINInput voltage, IN4.55.5V
Input voltage, logic-level inputs, EN, CTL1, CTL2, CTL3, ILIM_SEL05.5V
Input voltage, data line inputs, DP_IN, DM_IN, DP_OUT, DM_OUT0VINV
VIHHigh-level input voltage, EN, CTL1, CTL2, CTL3, ILIM_SEL1.8V
VILLow-level input voltage, EN, CTL1, CTL2, CTL3, ILIM_SEL0.8V
Continuous current, data line inputs, SDP or CDP mode, DP_IN to DP_OUT, DM_IN to DM_OUT±30mA
Continuous current, data line inputs, BC1.2 DCP mode, DP_IN to DM_IN±15mA
IOUTContinuous output current, OUTTJ = –40°C to 125°C02.5A
TJ = –40°C to 115°C03.0
Continuous output sink current, FAULT, STATUS010mA
RILIM_XXCurrent-limit set resistors15.4750
TJOperating virtual junction temperature–40125°C

Thermal Information

THERMAL METRIC(1)TPS2547UNIT
RTE (WQFN)
16 PINS
RθJAJunction-to-ambient thermal resistance53.4°C/W
RθJC(top)Junction-to-case (top) thermal resistance51.4°C/W
RθJBJunction-to-board thermal resistance17.2°C/W
ψJTJunction-to-top characterization parameter3.7°C/W
ψJBJunction-to-board characterization parameter20.7°C/W
RθJC(bot)Junction-to-case (bottom) thermal resistance3.9°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Electrical Characteristics

Unless otherwise noted: –40 ≤ TJ ≤ 125°C, 4.5 V ≤ VIN ≤ 5.5 V, VEN = VIN, VILIM_SEL = VIN, VCTL1 = VCTL2 = VCTL3 = VIN. RFAULT = RSTATUS = 10 kΩ, RILIM_HI = 20 kΩ, RILIM_LO = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SWITCH
RDS(on)ON resistance(1)TJ = 25°C, IOUT = 2 A7384
–40°C ≤ TJ ≤ 85°C, IOUT = 2 A73105
–40°C ≤ TJ ≤ 125°C, IOUT = 2 A73120
trOUT voltage rise timeVIN = 5 V, CL = 1 µF, RL = 100 Ω (see Figure 23 and Figure 24)0.711.6ms
tfOUT voltage fall time0.20.350.5
tonOUT voltage turnon timeVIN = 5 V, CL = 1 µF, RL = 100 Ω (see Figure 23 and Figure 25)2.74ms
toffOUT voltage turnoff time1.73
IREVReverse leakage currentVOUT = 5.5 V, VIN = VEN = 0 V, –40 ≤ TJ ≤ 85°C,
Measure IOUT
2µA
DISCHARGE
RDCHGOUT discharge resistance400500630Ω
tDCHG_LLong OUT discharge hold timeTime VOUT < 0.7 V (see Figure 26)1.322.9s
tDCHG_SShort OUT discharge hold timeTime VOUT < 0.7 V (see Figure 26)205310450ms
EN, ILIMSEL, CTL1, CTL2, CTL3 INPUTS
Input pin rising logic threshold voltage11.351.7V
Input pin falling logic threshold voltage0.851.151.45
Hysteresis(2)200mV
Input currentPin voltage = 0 V or 5.5 V–0.50.5µA
ILIMSEL CURRENT LIMIT
IOSOUT short-circuit current limit(1)VILIM_SEL = 0 V, RILIM_LO = 210 kΩ213250287mA
VILIM_SEL = 0 V, RILIM_LO = 80.6 kΩ598650708
VILIM_SEL = 0 V, RILIM_LO = 22.1 kΩ220023652530
VILIM_SEL = VIN, RILIM_HI= 20 kΩ242526102800
VILIM_SEL = VIN, RILIM_HI = 16.9 kΩ287530853300
VILIM_SEL = VIN, RILIM_HI = 15.4 kΩ, TJ = –40°C to 115°C315033753600
tIOSResponse time to OUT short-circuit(2)VIN = 5 V, R = 0.1Ω, lead length = 2 inches
(see Figure 27)
1.5µs
SUPPLY CURRENT
IIN_OFFDisabled IN supply currentVEN = 0 V, VOUT = 0 V, –40 ≤ TJ ≤ 85°C0.12µA
IIN_ONEnabled IN supply currentVCTL1 = VCTL2 = VIN, VCTL3 = 0 V, VILIM_SEL = 0 V165220µA
VCTL1 = VCTL2 = VCTL3 = VIN, VILIM_SEL = 0 V175230
VCTL1 = VCTL2 = VIN, VCTL3 = 0 V, VILIM_SEL = VIN185240
VCTL1 = VCTL2 = VIN, VCTL3 = VIN, VILIM_SEL = VIN195250
VCTL1 = 0 V, VCTL2 = VCTL3 = VIN215270
UNDERVOLTAGE LOCKOUT
VUVLOIN rising UVLO threshold voltage3.94.14.3V
Hysteresis(2)100mV
FAULT
Output low voltageIFAULT = 1 mA100mV
OFF-state leakageVFAULT = 5.5 V1µA
Overcurrent FAULT rising and falling deglitch58.212ms
STATUS
Output low voltageISTATUS = 1 mA100mV
OFF-state leakageVSTATUS = 5.5 V1µA
THERMAL SHUTDOWN
Thermal shutdown threshold155°C
Thermal shutdown threshold in current-limit135
Hysteresis(2)20
Pulse-testing techniques maintain junction temperature close to ambient temperature; Thermal effects must be taken into account separately.
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.

Electrical Characteristics: High-Bandwidth Switch

Unless otherwise noted: –40 ≤ TJ ≤ 125°C, 4.5 V ≤ VIN ≤ 5.5 V, VEN = VIN, VILIM_SEL = VIN, VCTL1 = VCTL2 = VCTL3 = VIN. RFAULT = RSTATUS = 10 kΩ, RILIM_HI = 20 kΩ, RILIM_LO = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
HIGH-BANDWIDTH ANALOG SWITCH
DP/DM switch ON resistanceVDP/DM_OUT = 0 V, IDP/DM_IN = 30 mA24Ω
VDP/DM_OUT = 2.4 V, IDP/DM_IN = –15 mA36
Switch resistance mismatch between
DP / DM channels
VDP/DM_OUT = 0 V, IDP/DM_IN = 30 mA0.050.15Ω
VDP/DM_OUT = 2.4 V, IDP/DM_IN = –15 mA0.050.15
DP/DM switch OFF-state capacitance(1)VEN= 0 V, VDP/DM_IN = 0.3 V, Vac = 0.6 Vpk–pk,
f = 1 MHz
33.6pF
DP/DM switch ON-state capacitance(2)VDP/DM_IN = 0.3 V, Vac = 0.6 Vpk-pk, f = 1 MHz5.46.2pF
OIRROFF-state isolation(3)VEN= 0 V, f = 250 MHz33dB
XTALKON-state cross channel isolation(3)f = 250 MHz52dB
OFF-state leakage currentVEN = 0 V, VDP/DM_IN = 3.6 V, VDP/DM_OUT = 0 V, measure IDP/DM_OUT0.11.5µA
BWBandwidth (–3 dB)(3)RL = 50 Ω2.6GHz
tpdPropagation delay(3)0.25ns
tSKSkew between opposite transitions of the same port (tPHL – tPLH)0.10.2ns
The resistance in series with the parasitic capacitance to GND is typically 250 Ω.
The resistance in series with the parasitic capacitance to GND is typically 150 Ω
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.

Electrical Characteristics: Charging Controller

Unless otherwise noted: –40 ≤ TJ ≤ 125°C, 4.5 V ≤ VIN ≤ 5.5 V, VEN = VIN, VILIM_SEL = VIN, VCTL1 = 0 V, VCTL2 = VCTL3 = VIN. RFAULT = RSTATUS = 10 kΩ, RILIM_HI = 20 kΩ, RILIM_LO = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SHORTED MODE (BC1.2 DCP)
DP_IN / DM_IN shorting resistanceVCTL1 = VIN, VCTL2 = VCTL3 = 0 V125200Ω
1.2 V MODE
DP_IN /DM_IN output voltageVCTL1 = VIN, VCTL2 = VCTL3 = 0 V1.191.251.31V
DP_IN /DM_IN output impedance607594
DIVIDER1 MODE
DP_IN divider1 output voltageVCTL1 = VIN, VCTL2 = VCTL3 = 0 V1.922.1V
DM_IN divider1 output voltage2.572.72.84V
DP_IN output impedance810.512.5
DM_IN output impedance810.512.5
DIVIDER2 MODE
DP_IN divider2 output voltageIOUT = 1 A2.572.72.84V
DM_IN divider2 output voltage1.922.1V
DP_IN output impedance810.512.5
DM_IN output impedance810.512.5
CHARGING DOWNSTREAM PORT
VDM_SRCDM_IN CDP output voltageVCTL1 = VCTL2 = VCTL3 = VINVDP_IN = 0.6 V,
–250 µA < IDM_IN < 0 µA
0.50.60.7V
VDAT_REFDP_IN rising lower window threshold for VDM_SRC activationVCTL1 = VCTL2 = VCTL3 = VIN0.250.4V
Hysteresis(1)50mV
VLGC_SRCDP_IN rising upper window threshold for VDM_SRC de-activation0.81V
Hysteresis(1)100mV
IDP_SINKDP_IN sink currentVCTL1 = VCTL2 = VCTL3 = VINVDP_IN = 0.6 V4070100µA
LOAD DETECT – NON-POWER WAKE
ILDIOUT rising load detect current thresholdVCTL1 = VCTL2 = VCTL3 = VIN635700765mA
Hysteresis(1)50mA
tLD_SETLoad detect set time140200275ms
Load detect reset time1.934.2s
LOAD DETECT – POWER WAKE
IOS_PWPower wake short-circuit current limitVCTL1 = VCTL2 = 0 V, VCTL3 = VIN325578mA
IOUT falling power wake reset current detection threshold234567mA
Reset current hysteresis(1)5mA
Power wake reset time10.71520.6s
These parameters are provided for reference only and do not constitute part of Texas Instrument's published device specifications for purposes of Texas Instrument's product warranty.

Typical Characteristics

TPS2547 G001_SLVSBA6.png Figure 1. Power Switch ON Resistance vs Temperature
TPS2547 G003_SLVSBA6.png Figure 3. OUT Discharge Resistance vs Temperature
TPS2547 G005_SLVSBA6.png Figure 5. Disabled in Supply Current vs Temperature
TPS2547 G007_SLVSBA6.png Figure 7. Enabled in Supply Current - CDP vs Temperature
TPS2547 G009_SLVSBA6.png Figure 9. Status and Fault Output Low Voltage
vs Sinking Current
TPS2547 wav16_lvsag2.gif Figure 11. OFF-State Data Switch Isolation vs Frequency
TPS2547 G013_SLVSBA6.gif Figure 13. Eye Diagram Using USB Compliance Test Pattern (With No Switch)
TPS2547 G015_SLVSBA6.png Figure 15. IOUT Rising Load Detect Threshold and Out Short-Circuit Current Limit vs Temperature
TPS2547 G017_SLVSBA6.png Figure 17. Power Wake Current Limit vs Temperature
TPS2547 G022_SLVSBA6.gif Figure 19. Turnoff Response
TPS2547 G024_SLVSBA6.gif Figure 21. Device Enabled Into Short-Circuit - Thermal Cycling
TPS2547 G002_SLVSBA6.png Figure 2. Reverse Leakage Current vs Temperature
TPS2547 G004_SLVSBA6.png Figure 4. OUT Short-Circuit Current Limit vs Temperature
TPS2547 G006_SLVSBA6.png Figure 6. Enabled in Supply Current - SDP vs Temperature
TPS2547 G008_SLVSBA6.png Figure 8. Enabled in Supply Current - DCP Auto
vs Temperature
TPS2547 wav15_lvsag2.gif Figure 10. Data Transmission Characteristics vs Frequency
TPS2547 wav17_lvsag2.gif Figure 12. ON-State Cross-Channel Isolation vs Frequency
TPS2547 G014_SLVSBA6.gif Figure 14. Eye Diagram Using USB Compliance Test Pattern (With Data Switch)
TPS2547 G016_SLVSBA6.png Figure 16. Load Detect Set Time vs Temperature
TPS2547 G021_SLVSBA6.gif Figure 18. Turnon Response
TPS2547 G023_SLVSBA6.gif Figure 20. Device Enabled Into Short-Circuit
TPS2547 G025_SLVSBA6.gif Figure 22. Short-Circuit to Full Load Recovery