SLVSDG8B Data sheet

SLVSDG8B April 2016 – June 2017 TPS25740 , TPS25740A

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

RGE|24
- MPQF124G

Thermal pad, mechanical data (Package|Pins)

RGE|24
- QFND136Y

Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Pin Voltage (sustained)	VDD , EN12V, EN9V, CTL1, CTL2, UFP, PCTRL, CC1, CC2	–0.3	6	V
	VTX⁽²⁾	–0.3	2.1	V
	VAUX⁽²⁾	–0.3	4.5	V
	GD ⁽³⁾	–0.3	7	V
	HIPWR, PSEL, DVDD ⁽²⁾	–0.3	2.1	V
	GDNG⁽²⁾	–0.5	40	V
	VBUS,VPWR, ISNS, DSCG, GDNS	–0.5	30	V
Pin Voltage (transient for 1ms)	VBUS,VPWR, ISNS, DSCG, GDNS	–1.5	30	V
Pin-to-pin voltage	V_(GDNG) – V_(GDNS)	–0.3	20	V
	AGND to GND	–0.3	0.3	V
	ISNS to VBUS	–0.3	0.3	V
Sinking current (average)	CTL1, CTL2, UFP		8	mA
	GD		100	µA
	DSCG		10	mA
Sinking current (transient, 50 ms pulse 0.25% duty cycle)	DSCG		375	mA
Current sourcing	VTX	Internally limited		mA
	CC1, CC2	Internally limited		mA
	VAUX	0	25	µA
Operating junction temperature range, T_J		–40	125	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Do not apply voltage to these pins.

(3) Voltage allowed to rise above Absolute Maximum provided current is limited.

7.2 ESD Ratings⁽³⁾

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2500	V
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000
		IEC ⁽⁴⁾ 61000-4-2 contact discharge, CC1, CC2	±8000
		IEC ⁽⁴⁾ 61000-4-2 air-gap discharge, CC1, CC2	±15000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

(4) These results were passing limits that were obtained on an application-level test board. Individual results may vary based on implementation. Surges per IEC61000-4-2, 1999 applied between CC1/CC2 and ground of TPS25740EVM-741 and TPS25740AEVM-741

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
V_IN	Supply Voltage	VDD	0		5.5	V
V_IN	Supply Voltage	VPWR	4.65		25	V
V_I	Applied Voltage	EN12V, EN9V, PCTRL, CC1, CC2, CTL1, CTL2	0		5.5	V
		GD	0		6.5	V
		DSCG, GDNS, VBUS	0		25	V
		HIPWR, PSEL	0		DVDD	V
V_I	Pin-to-pin voltage	ISNS - VBUS	–0.1		0.1	V
V_IH	High-Level Input Voltage	EN12V, EN9V	1.4			V
		PCTRL	2			V
		GD	2			V
V_IL	Low-Level Input Voltage	EN12V, EN9V			0.5	V
		PCTRL			1.6	V
		GD			1.6	V
I_S	Sinking Current	CTL1, CTL2, UFP			5	mA
		GD			80	µA
		DSCG, transient sinking current 50 ms pulse, 0.25% duty cycle			350	mA
		DSCG, average			5	mA
C_S	Shunt capacitance	CC1, CC2 (C_(RX))	200	560	600	pF
		VBUS (C_(PDIN))			10	µF
		DVDD (C_(DVDD))	0.198	0.22	0.242	µF
		VAUX (C_(VAUX))	0.09	0.1	0.11	µF
		VTX (C_(VTX))	0.09	0.10	0.11	µF
		VDD (C_(VDD))	0.09			µF
R_S	Sense resistance	Configured for 3 A		5	6.4	mΩ
R_S	Sense resistance	Configured for 5 A		5	5.8	mΩ
R_(PUD)	Pull up/down resistance	HIPWR, PSEL (direct to GND or direct to DVDD)	0		1	kΩ
R_(PUD)	Pull up/down resistance	HIPWR, PSEL (R_(SEL))	80	100	120	kΩ
R_(DSCG)	Series resistance	Maximum VBUS voltage of 25 V	80			Ω
		Maximum VBUS voltage of 15 V	43			Ω
		Maximum VBUS voltage of 6 V	20			Ω
T_J	Operating junction temperature		-40		125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS25740 TPS25740A	UNIT
		RGE (VQFN)
		24 PINS
R_θJA	Junction-to-ambient thermal resistance	33	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	32.6	°C/W
R_θJB	Junction-to-board thermal resistance	10	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	°C/W
ψ_JB	Junction-to-board characterization parameter	10	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.6	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ T_J ≤ 125°C; 3 ≤ VDD ≤ 5.5 V, 4.65 V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND; VAUX, VTX, bypassed with 0.1 µF, DVDD bypassed with 0.22 µF, EN12V = GND and EN9V = GND; all other pins open (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
Voltage Comparator (VBUS)
V_{(VBUS_RTH)}	VBUS Threshold (Rising voltage)		4.25	4.45	4.65	V
V_{(VBUS_FTH)}	VBUS Threshold (Falling voltage)		3.5	3.7	3.9	V
	VBUS Threshold (Hysteresis)			0.75		V
Power Supply (VDD, VPWR)
V_{(VDD_TH)}	VDD UVLO threshold	Rising voltage	2.8	2.91	2.97	V
		Falling voltage	2.8	2.86	2.91
		Hysteresis, comes into effect once the rising threshold is crossed.		0.05
V_{(VPWR_RTH)}	VPWR UVLO threshold rising	Rising voltage	4.2	4.45	4.65	V
V_{(VPWR_FTH)}	VPWR UVLO threshold falling	Falling voltage	3.5	3.7	3.9	V
	VPWR UVLO threshold hysteresis	Hysteresis, comes into effect once the rising threshold is crossed.		0.75		V
	Supply current drawn from VDD in sleep mode	VPWR = 0 V, VDD = 5 V, CC1 and CC2 pins are open.		9.2	20	µA
	Supply current drawn from VDD in sleep mode	VPWR = 0 V, VDD = 5 V,CC1 pin open, CC2 pin tied to GND.		94	150	µA
	Supply current drawn from VPWR in sleep mode	VPWR = 5 V, VDD = 0 V, CC1 and CC2 pins are open.		8.5	15	µA
	Supply current drawn from VPWR in sleep mode	VPWR = 5 V, VDD = 0 V, CC1 pin open, CC2 pin tied to GND.		90	140	µA
I_(SUPP)	Operating current while sink attached	PD Sourcing active, VBUS = 5 V, VPWR = 5 V, VDD = 3.3 V	1	1.8	3	mA
Over/Under Voltage Protection (VBUS)
V_(FOVP)	Fast OVP threshold, always enabled	5 V PD contract	5.8	6.05	6.3	V
		12 V PD contract (TPS25740)	13.2	13.75	14.3	V
		20 V PD contract (TPS25740)	22.1	23.05	24.0	V
		9 V PD contract (TPS25740A)	10.1	10.55	11.0	V
		15 V PD contract (TPS25740A)	16.2	16.95	17.7	V
V_(SOVP)	Slow OVP threshold, disabled during voltage transitions. (See Figure 1)	5 V PD contract	5.5	5.65	5.8	V
		12 V PD contract (TPS25740)	13.1	13.4	13.7	V
		20 V PD contract (TPS25740)	21.5	22.0	22.5	V
		9 V PD contract (TPS25740A)	10	10.2	10.4	V
		15 V PD contract (TPS25740A)	16.3	16.5	17	V
V_(SUVP)	UVP threshold, disabled during voltage transitions (See Figure 1)	5 V PD contract	3.5	3.65	3.8	V
		12 V PD contract (TPS25740)	9.2	9.45	9.7	V
		20 V PD contract (TPS25740)	15.7	16.1	16.5	V
		9 V PD contract (TPS25740A)	6.8	6.95	7.1	V
		15 V PD contract (TPS25740A)	11.7	11.95	12.2	V
VAUX
V_(VAUX)	Output voltage	0 ≤ I_(VAUX) ≤ I_(VAUXEXT)	2.875	3.2	4.1	V
	VAUX Current limit		1		5	mA
I_(VAUXEXT)	External load that may be applied to VAUX.				25	µA
DVDD
V_(DVDD)	Output voltage	0 mA ≤ I_(DVDD) ≤ 35 mA, CC1 or CC2 pulled to ground via 5.1 kΩ, or both CC1 and CC2 pulled to ground via 1 kΩ	1.75	1.85	1.95	V
	Load Regulation	Overshoot from V_(DVDD), 10-mA minimum, 0.198-µF bypass capacitor	1.7		2	V
	Current limit	DVDD tied to GND	40		150	mA
VTX
	Output voltage	Not transmitting or receiving, 0 to 2 mA external load	1.050	1.125	1.200	V
	Current Limit	VTX tied to GND	2.5		10	mA
Gate Driver Disable (GD)
V_{(GD_TH)}	Input enable threshold voltage	Rising voltage	1.64	1.725	1.81	V
V_{(GD_TH)}	Input enable threshold voltage	Hysteresis		0.15		V
V_(GDC)	Internal clamp voltage	I_(GD) = 80 µA	6.5	7	8.5	V
R_(GD)	Internal pulldown resistance	From 0 V to 6 V	3	6	9.5	MΩ
Discharge (DSCG) ⁽¹⁾⁽²⁾
V_(DSCGT)	ON state (linear)	I_(DSCG) = 100 mA	0.15	0.42	1	V
I_(DSCGT)	ON state (saturation)	V_(DSCG) = 4 V, pulsed mode operation	220	553	1300	mA
R_(DSCGB)	Discharge bleeder	While CC1 is pulled down by 5.1 kΩ and CC2 is open, V_(DSCG) = 25 V	6.6	8.2	10	kΩ
	Leakage current	0 V ≤ V_(DSCG) ≤ 25 V			2	µA
N-ch MOSFET Gate Driver (GDNG,GDNS)
I_(GDNON)	Sourcing current	0 V ≤ V_(GDNS) ≤ 25 V, 0 V ≤ V_(GDNG) – V_(GDNS) ≤ 6 V	13.2	20	30	µA
V_(GDNON)	Sourcing voltage while enabled (V_(GDNG)– V_(GDNS))	0 V ≤ V_(GDNS) ≤ 25 V, I_(GDNON) ≤ 4 µA, VPWR = 0 V	7		12	V
V_(GDNON)	Sourcing voltage while enabled (V_(GDNG)– V_(GDNS))	0 V ≤ V_(GDNS) ≤ 25 V, I_(GDNON) ≤ 4 µA, VDD = 0 V	8.5		12	V
R_(GDNGOFF)	Sinking strength while disabled	V_(GDNG) – V_(GDNS)= 0.5 V, 0 ≤ V_(GDNS) ≤ 25 V		150	300	Ω
	Sinking strength UVLO (safety)	VDD = 1.4 V, V_(GDNG) = 1 V, V_(GDNS) = 0 V, VPWR = 0 V		145		µA
	Sinking strength UVLO (safety)	VPWR = 1.4 V, V_(GDNG) = 1 V, V_(GDNS) = 0 V, VDD = 0 V		145		µA
	Off-state leakage	V_(GDNS) = 25 V, V_(GDNG) open			7	µA
Power Control Input (PCTRL)
V_{(PCTRL_TH)}	Threshold voltage⁽³⁾	Voltage rising	1.65	1.75	1.85	V
V_{(PCTRL_TH)}	Threshold voltage⁽³⁾	Hysteresis		100		mV
	Input resistance	0 V ≤ V_(PCTRL) ≤ V_(VAUX)	1.5	2.9	6	MΩ
Voltage Select (HIPWR), Power Select (PSEL)⁽⁴⁾
	Leakage current	0 V ≤ V_(HIPWR) ≤ V_(DVDD), 0 V ≤ V_(PSEL) ≤ V_(DVDD)	–1		1	µA
Port Status and Voltage Control (CTL1, CTL2, UFP)⁽⁵⁾
V_OL	Output low voltage	I_OL = 4 mA sinking			0.4	V
	Leakage Current ⁽⁶⁾	In Hi-Z state, 0 ≤ V_(CTLx) ≤ 5.5 V or 0 ≤ V_UFP ≤ 5.5V	–0.5		0.5	µA
Enable 9 V, 12 V Capability (EN9V, EN12V)
	Input low threshold voltage				0.585	V
	Input high threshold voltage		1.225			V
	Input hysteresis			0.25		V
Transmitter Specifications (CC1, CC2)
R_TX	Output resistance (zDriver from USB PD in Documentation Support)	During transmission	33	45	75	Ω
V_(TXHI)	Transmit high voltage	External Loading per Figure 25	1.05	1.125	1.2	V
V_(TXLO)	Transmit low voltage	External Loading per Figure 25	–75		75	mV
Receiver Specifications (CC1, CC2)
V_(RXHI)	Receive threshold (rising)		800	840	885	mV
V_(RXLO)	Receive threshold (falling)		485	525	570	mV
	Receive threshold (Hysteresis)			315		mV
V_(INT)	Amplitude of interference that can be tolerated	Interference is 600 kHz square wave, rising 0 to 100 mV.			100	mV
V_(INT)	Amplitude of interference that can be tolerated	Interference is 1 MHz sine wave			1	V_PP
DFP Specifications (CC1, CC2)
V_(DSTD)	Detach threshold when cable is detached.	In standard DFP mode⁽⁷⁾, voltage rising	1.52	1.585	1.65	V
V_(DSTD)		Hysteresis		0.02		V
V_(D1.5)		In 1.5 A DFP mode⁽⁸⁾, voltage rising	1.52	1.585	1.65	V
V_(D1.5)		Hysteresis		0.02		V
V_(D3.0)		In 3 A DFP mode⁽⁹⁾, voltage rising	2.50	2.625	2.75	V
V_(D3.0)		Hysteresis		0.05		V
V_(OCN)	Unloaded output voltage on CC pin	normal mode	2.7		4.35	V
V_(OCDS)	Unloaded output voltage on CC pin	VPWR = 0 V (in UVLO) or in sleep mode	1.8		5.5	V
I_(RPSTD)	Loaded output current while connected through CCx	In standard DFP mode1, CCy open, 0 V ≤ V_CCx ≤ 1.5 V (vRd)	64	80	96	µA
I_(RP1.5)		In 1.5 A DFP mode 2, CCy open, 0 V ≤ V_CCx ≤ 1.5 V (vRd)	166	180	194	µA
I_(RP3.0)		In 3 A DFP mode 3, CCy open, 0 V ≤ V_CCx ≤ 1.5 V (vRd)	304	330	356	µA
V_(RDSTD)	Ra, Rd detection threshold (falling)	In standard DFP mode1, 0 V ≤ V_CCx ≤ 1.5 V (vRd)	0.15	0.19	0.23	V
V_(RDSTD)		Hysteresis		0.02		V
V_(RD1.5)		In 1.5 A DFP mode2, CCy open 0 V ≤ V_CCx ≤ 1.5 V (vRd)	0.35	0.39	0.43	V
V_(RD1.5)		Hysteresis		0.02		V
V_(RD3.0)		In 3 A DFP mode3, CCy open 0 V ≤ V_CCx ≤ 1.5 V (vRd)	0.75	0.79	0.83	V
V_(RD3.0)		Hysteresis		0.02		V
V_(WAKE)	Wake threshold (rising and falling), exit from sleep mode	VPWR = 4.65 V , 0 V ≤ V_DD ≤ 3 V	1.6		3.0	V
I_(DSDFP)	Output current on CCx in sleep mode to detect Ra removal.	CCx = 0V, CCy floating	40	73	105	µA
OverCurrent Protection (ISNS, VBUS)
V_I(TRIP)	Current trip shunt voltage	Specified as V_(ISNS)-V_(VBUS). 3.5 V⁽¹⁰⁾ ≤ VBUS ≤ 25 V
		HIPWR: 5 A not enabled	19.2		22.6	mV
		HIPWR = DVDD (5 A enabled)	29		34	mV
OTSD
T_J1	Die Temperature (Analog)⁽¹¹⁾	T_J ↑	125	135	145	°C
T_J1	Die Temperature (Analog)⁽¹¹⁾	Hysteresis		10		°C
T_J2	Die Temperature (Analog) ⁽¹²⁾	T_J ↑	140	150	163	°C
T_J2	Die Temperature (Analog) ⁽¹²⁾	Hysteresis		10		°C

(1) If T_J1 is perceived to have been exceeded an OTSD occurs and the discharge FET is disabled.

(2) The discharge pull-down is not active in the sleep mode.

(3) When voltage on the PCTRL pin is less than V_{(PCTRL_TH)}, the amount of power advertised is reduced by half.

(4) Leaving HIPWR or PSEL open is an undetermined state and leads to unpredictable behavior.

(5) These pins are high-z during a UVLO, reset, or in Sleep condition.

(6) The pins were designed for less leakage, but testing only verifies that the leakage does not exceed 0.5 µA.

(7) Standard DFP mode is active after a USB Type-C sink, debug accessory, or audio accessory is attached until the first USB PD message is transmitted (after GDNG has been enabled).

(8) 1.5 A DFP mode is active after a USB PD message is received.

(9) 3 A DFP mode is active after GDNG has been enabled until a USB PD message is received.

(10) Common mode minimum aligns to VBUS UVLO. VBUS must be above its UVLO for the OCP function to be active.

(11) When T_J1 trips a hard reset is transmitted and discharge is disabled, but the bleed discharge is not disabled.

(12) T_J2 trips only when some external heat source drives the temperature up. When it trips the DVDD, and VAUX power outputs are turned off.

7.6 Timing Requirements

			MIN	NOM	MAX	UNIT
t_FOVPDG	Deglitch for fast over-voltage protection			5		µs
t_OCP	Deglitch Filter for over-current protection				15	µs
	Time power is applied until CC1 and CC2 pull-ups are applied.	V_(VPWR) > V_{(VPWR_TH)} OR V_(VDD)> V_{(VDD_TH)}		2.5	4	ms
t_CC	Falling/Rising voltage deglitch time for detection on CC1 and CC2			120		µs
Transmitter Specifications (CC1, CC2)
t_UI	Bit unit Interval		3.05	3.3	3.70	µs
	Rise/fall time, t_Fall and t_Rise (refer to USB PD in Documentation Support)	External Loading per Figure 25	300		600	ns

7.7 Switching Characteristics

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_VP	Delay from enabling external NFET until under-voltage and OCP protection are enabled	VBUS = GND		190		ms
t_STL	Source settling time, time from CTL1 and CTL2 being changed until a PS_RDY USB PD message is transmitted to inform the sink is may draw full current. (refer to USB PD in Documentation Support)			260		ms
t_SR	Time that GDNG is disabled after a hard reset. This is t_SrcRecover. (refer to USB PD in Documentation Support)	T_J > T_J1		765		ms
t_HR	Time after hard reset is transmitted until GDNG is disabled. This is t_PSHardReset. (refer to USB PD in Documentation Support)			30		ms
t_CCDeb	Time until UFP is pulled low after sink attachment, this is the USB Type-C required debounce time for attachment detection called t_CCDebounce. (refer to USB Type-C in Documentation Support)			185		ms
t_ST	Delay after sink request is accepted until CTL1 and/or CTL2 is changed. This is called t_{SnkTransition}. (refer to USB PD in Documentation Support)			30		ms
t_FLT	The time in between hard reset transmissions in the presence of a persistent supply fault.	GD = GND or VPWR=GND, sink attached		1395		ms
t_SH	The time in between retries (hard reset transmissions) in the presence of a persistent VBUS short.	VBUS = GND, sink attached		985		ms
t_ON	The time from UFP being pulled low until a hard reset is transmitted. Designed to be greater than t_SrcTurnOn. (refer to USB PD in Documentation Support)	GD = 0 V or VPWR = 0 V		600		ms
	Retry interval if USB PD sink stops communicating without being removed or if sink does not communicate after a fault condition. Time GDNG remains enabled before a hard reset is transmitted. This is the t_NoResponse time. (refer to USB PD in Documentation Support)	Sink attached		4.8		s
t_DVDD	Delay before DVDD is driven high	After sink attached			5	ms
t_GDoff	Turnoff delay, time until V_(GDNG) is below 10% of its initial value after the GD pin is low.	V_GD: 5 V → 0 V in < 0.5 µs.			5	µs
t_FOVP	Response time when VBUS exceeds the fast-OVP threshold	VBUS ↑ to GDNG OFF (V_(GDNG)below 10% its initial value)			30	µs
	OCP large signal response time	5 A enabled, V_(ISNS) -V_(VBUS): 0 V → 42 mV measured to GDNG transition start.			30	µs
	Time until discharge is stopped after T_J1 is exceeded.	0 V ≤ V_(DSCG) ≤ 25 V			10	µs
	Digital output fall time	V_(PULLUP) = 1.8 V, C_L = 10 pF, R_(PULLUP) = 10 kΩ, V_(CTLx) or V_(UFP) : 70% V_PULLUP → 30% V_PULLUP	20		300	ps

Figure 1. Timing Illustration for t_VP, t_ST and t_STL, After Sink Attachment negotiation to 12 V then back to 5 V. V_(SOVP) and V_(SUVP) are Disabled Around Voltage Transitions.