SLVSDR6C June   2017  – March 2018 TPS25740B

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 VBUS Capacitance
      2. 8.1.2 USB Data Communications
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  ENSRC
      2. 8.3.2  USB Type-C CC Logic (CC1, CC2)
      3. 8.3.3  USB PD BMC Transmission (CC1, CC2, VTX)
      4. 8.3.4  USB PD BMC Reception (CC1, CC2)
      5. 8.3.5  Discharging (DSCG, VPWR)
        1. 8.3.5.1 Discharging after a Fault (VPWR)
      6. 8.3.6  Configuring Voltage Capabilities (HIPWR)
      7. 8.3.7  Configuring Power Capabilities (PSEL, PCTRL, HIPWR)
      8. 8.3.8  Gate Driver (GDNG, GDNS)
      9. 8.3.9  Fault Monitoring and Protection
        1. 8.3.9.1 Over/Under Voltage (VBUS)
        2. 8.3.9.2 Over-Current Protection (ISNS, VBUS)
        3. 8.3.9.3 System Fault Input (GD, VPWR)
      10. 8.3.10 Voltage Control (CTL1, CTL2,CTL3)
      11. 8.3.11 Sink Attachment Indicator (DVDD)
      12. 8.3.12 Power Supplies (VAUX, VDD, VPWR, DVDD)
      13. 8.3.13 Grounds (AGND, GND)
      14. 8.3.14 Output Power Supply (DVDD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
      2. 8.4.2 Checking VBUS at Start Up
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 System-Level ESD Protection
      2. 9.1.2 Using ENSRC to Enable the Power Supply upon Sink Attachment
      3. 9.1.3 Use of GD Internal Clamp
      4. 9.1.4 Resistor Divider on GD for Programmable Start Up
      5. 9.1.5 Selection of the CTL1, CTL2, and CTL3 Resistors (R(FBL1), R(FBL2), and R(FBL3))
      6. 9.1.6 Voltage Transition Requirements
      7. 9.1.7 VBUS Slew Control using GDNG C(SLEW)
      8. 9.1.8 Tuning OCP using RF and CF
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application, A/C Power Source (Wall Adapter)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power Pin Bypass Capacitors
          2. 9.2.1.2.2 Non-Configurable Components
          3. 9.2.1.2.3 Configurable Components
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Typical Application, D/C Power Source
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Power Pin Bypass Capacitors
          2. 9.2.2.2.2 Non-Configurable Components
          3. 9.2.2.2.3 Configurable Components
        3. 9.2.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 D/C Power Source (Power Hub)
      2. 9.3.2 A/C Power Source (Wall Adapter)
      3. 9.3.3 Dual-Port A/C Power Source (Wall Adaptor)
      4. 9.3.4 D/C Power Source (Power Hub with 3.3 V Rail)
  10. 10Power Supply Recommendations
    1. 10.1 VDD
    2. 10.2 VPWR
  11. 11Layout
    1. 11.1 Port Current Kelvin Sensing
    2. 11.2 Layout Guidelines
      1. 11.2.1 Power Pin Bypass Capacitors
      2. 11.2.2 Supporting Components
    3. 11.3 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.2.3 Configurable Components

  • C(RX): Choose C(RX) between 200 pF and 600 pF. A 560 pF, 50 V, ±5% COG/NPO ceramic is recommended for both CC1 and CC2 pins.
  • Q1: For a 3 A application, an N-Channel MOSFET with RDS(on) in the 10 mΩ range is sufficient. BV(DSS) should be rated for 30 V for applications delivering 20 V, and 25 V for 15 V applications. For this application, the TI CSD17579Q3A (SLPS527) NexFET™ is suitable.
  • RS: TPS25740B OCP set point thresholds are targeted towards a 5 mΩ, ±1% sense resistor. Power dissipation for RS at 3 A load is approximately 45 mW.
  • R(DSCG): The minimum value of R(DSCG) is chosen based on the application VBUS (max) and I(DSCGT). For VBUS (max) = 15 V and I(DSCGT) = 350 mA, RDS(CG(min)) = 42.9 Ω. The size of the external resistor can then be chosen based on the capacitive load that needs to be discharged and the maximum allowed discharge time of 265 ms. Typically, a 120 Ω, 0.5 W resistor provides suitable performance.
  • RF/CF: Not used
  • C(PDIN): The requirement for C(PDIN) is 10 µF maximum. A 6.8 µF, 25 V, ±10% X5R or X7R ceramic capacitor is suitable for most applications.
  • D(VBUS): D(VBUS) provides reverse transient protection during large transient conditions when inductive loads are present. A Schottky diode with a V(RRM) rating of 30 V in a SMA package such as the B340A-13-F provides suitable reverse voltage clamping performance.
  • C(SLEW): To achieve a slew rate from zero to 5 V of less than 30 mV / µs using the typical GDNG current of 20 µA then C(SLEW) (nF) > 20 µA / 30 mV / µs = 0.67 nF be used. Choosing C(SLEW) = 10 nF yields a ramp rate of 2 mV / µs.
  • R(FBL1)/R(FBL2)/R(FBL3): In this design example, R(FBU) = 49.9 kΩ and R(FBL) = 9.53 kΩ. The feedback error amplifier VREF = 0.8 V. Using the equations for R(FBL2) (Equation 5 and Equation 6) provide a calculated value of 9.9 kΩ and a selected value of 9.76 kΩ. In similar fashion for R(FBL1), a calculated value of 6.74 kΩ and a selected value of 6.65 kΩ is provided. Lastly for R(FBL3), the calculated value is 8.1 kΩ with a selected value of 8.06 kΩ.
  • C(SLU)/C(SLL): The value of C(SLU) is calculated based on the desired 95% slew rate using Equation 13 and Equation 14. Choose a 22 nF capacitor for C(SLU). Choose a 100 nF capacitor for C(SLL).