SLUSCT1 June 2017 TPS53681

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Supply: Currents, UVLO, and Power-On Reset
    6. 6.6 References: DAC and VREF
    7. 6.7 Voltage Sense: AVSP and BVSP, AVSN and BVSN
    8. 6.8 Telemetry
    9. 6.9 Input Current Sensing
    10. 6.10Programmable Loadline Settings
    11. 6.11Current Sense and Calibration
    12. 6.12Logic Interface Pins: AVR_EN, AVR_RDY, BVR_EN, BVR_RDY, RESET, VR_FAULT, VR_HOT
    13. 6.13I/O Timing
    14. 6.14PMBus Address Setting
    15. 6.15Overcurrent Limit Thresholds
    16. 6.16Switching Frequency
    17. 6.17Slew Rate Settings
    18. 6.18Ramp Selections
    19. 6.19Dynamic Integration and Undershoot Reduction
    20. 6.20Boot Voltage and TMAX Settings
    21. 6.21Protections: OVP and UVP
    22. 6.22Protections: ATSEN and BTSEN Pin Voltage Levels and Fault
    23. 6.23PWM: I/O Voltage and Current
    24. 6.24Dynamic Phase Add and Drop
    25. 6.25Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1Phase Interleaving and PWM Operation
        1. 7.3.1.1Setting the Load-Line (DROOP)
        2. 7.3.1.2Load Transitions
          1. 7.3.1.2.1VID Table
        3. 7.3.1.3Temperature and Fault Sensing
        4. 7.3.1.4AutoBalance™ Current Sharing
        5. 7.3.1.5Phase Configuration for Channel B
        6. 7.3.1.6RESET Function
    4. 7.4Device Functional Modes
    5. 7.5Programming
      1. 7.5.1 PMBus Connections
      2. 7.5.2 PMBus Address Selection
      3. 7.5.3 Supported Commands
      4. 7.5.4 Commonly Used PMBus Commands
      5. 7.5.5 Voltage, Current, Power, and Temperature Readings
        1. 7.5.5.1(88h) READ_VIN
        2. 7.5.5.2(89h) READ_IIN
        3. 7.5.5.3(8Bh) READ_VOUT
        4. 7.5.5.4(8Ch) READ_IOUT
        5. 7.5.5.5(8Dh) READ_TEMPERATURE_1
        6. 7.5.5.6(96h) READ_POUT
        7. 7.5.5.7(97h) READ_PIN
        8. 7.5.5.8(D4h) MFR_SPECIFIC_04
      6. 7.5.6 Input Current Sense and Calibration
        1. 7.5.6.1Measured Input Current Calibration
        2. 7.5.6.2(DAh) MFR_SPECIFIC_10
        3. 7.5.6.3(DCh) MFR_SPECIFIC_12
      7. 7.5.7 Output Current Sense and Calibration
        1. 7.5.7.1Reading Individual Phase Currents
          1. 7.5.7.1.1Reading Total Current
          2. 7.5.7.1.2Calibrating Current Measurements
        2. 7.5.7.2(38h) IOUT_CAL_GAIN
        3. 7.5.7.3(39h) IOUT_CAL_OFFSET
      8. 7.5.8 Output Voltage Margin Testing
        1. 7.5.8.1(01h) OPERATION
        2. 7.5.8.2(26h) VOUT_MARGIN_LOW
        3. 7.5.8.3(25h) VOUT_MARGIN_HIGH
      9. 7.5.9 Loop Compensation
        1. 7.5.9.1(D7h) MFR_SPECIFIC_07
        2. 7.5.9.2(28h) VOUT_DROOP
      10. 7.5.10Converter Protection and Response
      11. 7.5.11Output Overvoltage Protection and Response
        1. 7.5.11.1(40h) VOUT_OV_FAULT_LIMIT
        2. 7.5.11.2(41h) VOUT_OV_FAULT_RESPONSE
      12. 7.5.12Maximum Allowed Output Voltage Setting
        1. 7.5.12.1(24h) VOUT_MAX
      13. 7.5.13Output Undervoltage Protection and Response
        1. 7.5.13.1(44h) VOUT_UV_FAULT_LIMIT
        2. 7.5.13.2(45h) VOUT_UV_FAULT_RESPONSE
      14. 7.5.14Minimum Allowed Output Voltage Setting
        1. 7.5.14.1(2Bh) VOUT_MIN
      15. 7.5.15Output Overcurrent Protection and Response
        1. 7.5.15.1(46h) IOUT_OC_FAULT_LIMIT
        2. 7.5.15.2(4Ah) IOUT_OC_WARN_LIMIT
        3. 7.5.15.3(47h) IOUT_OC_FAULT_RESPONSE
      16. 7.5.16Input Under-Voltage Lockout (UVLO)
        1. 7.5.16.1(35h) VIN_ON
      17. 7.5.17Input Over-Voltage Protection and Response
        1. 7.5.17.1(55h) VIN_OV_FAULT_LIMIT
        2. 7.5.17.2(56h) VIN_OV_FAULT_RESPONSE
      18. 7.5.18Input Undervoltage Protection and Response
        1. 7.5.18.1(59h) VIN_UV_FAULT_LIMIT
        2. 7.5.18.2(5Ah) VIN_UV_FAULT_RESPONSE
      19. 7.5.19Input Overcurrent Protection and Response
        1. 7.5.19.1(5Bh) IIN_OC_FAULT_LIMIT
        2. 7.5.19.2(5Dh) IIN_OC_WARN_LIMIT
        3. 7.5.19.3(5Ch) IIN_OC_FAULT_RESPONSE
      20. 7.5.20Over-Temperature Protection and Response
        1. 7.5.20.1(4Fh) OT_FAULT_LIMIT
        2. 7.5.20.2(51h) OT_WARN_LIMIT
        3. 7.5.20.3(50h) OT_FAULT_RESPONSE
      21. 7.5.21Dynamic Phase Shedding (DPS)
        1. 7.5.21.1(DEh) MFR_SPECIFIC_14
        2. 7.5.21.2(DFh) MFR_SPECIFIC_15
      22. 7.5.22NVM Programming
      23. 7.5.23NVM Security
        1. 7.5.23.1(FAh) MFR_SPECIFIC_42
      24. 7.5.24Black Box Recording
        1. 7.5.24.1(D8h) MFR_SPECIFIC_08
      25. 7.5.25Board Identification and Inventory Tracking
        1. 7.5.25.1(9Ah) MFR_MODEL
        2. 7.5.25.2(9Bh) MFR_REVISION
        3. 7.5.25.3(9Dh) MFR_DATE
      26. 7.5.26Status Reporting
        1. 7.5.26.1(78h) STATUS_BYTE
        2. 7.5.26.2(79h) STATUS_WORD
        3. 7.5.26.3(7Ah) STATUS_VOUT
        4. 7.5.26.4(7Bh) STATUS_IOUT
        5. 7.5.26.5(7Ch) STATUS_INPUT
        6. 7.5.26.6(7Dh) STATUS_TEMPERATURE
        7. 7.5.26.7(7Eh) STATUS_CML
        8. 7.5.26.8(80h) STATUS_MFR_SPECIFIC
  8. Applications, Implementation, and Layout
    1. 8.1Application Information
    2. 8.2Typical Application
      1. 8.2.1 6-phase, 0.9-V, 300-A Application and 2-phase 0.8-V, 90-A Application
        1. 8.2.1.1Schematic
        2. 8.2.1.2Design Requirements
        3. 8.2.1.3Detailed Design Procedure
          1. 8.2.1.3.1Choose Inductor
          2. 8.2.1.3.2Select the Per-Phase Valley Current Limit
          3. 8.2.1.3.3Set the Maximum Temperature Level (TMAX)
          4. 8.2.1.3.4Set USR Thresholds to Improve Load Transient Performance
        4. 8.2.1.4Inductor DCR and Shunt Current Sensing Design for Input Power
          1. 8.2.1.4.1Compensation Design
          2. 8.2.1.4.2Set PMBus Addresses
        5. 8.2.1.5Application Performance Plots
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
      1. 10.1.1Device Guidelines
      2. 10.1.2Power Stage Guidelines
    2. 10.2Layout Examples
  11. 11Device and Documentation Support
    1. 11.1Receiving Notification of Documentation Updates
    2. 11.2Community Resources
    3. 11.3Trademarks
    4. 11.4Electrostatic Discharge Caution
    5. 11.5Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Features

  • Conversion Input Voltage Range: 4.5 V to 17 V
  • 8-Bit DAC with Selectable 5 mV or 10 mV Resolution and Output Ranges from 0.25 V to 1.52 V or 0.5 to 2.8125 V for Dual Channels
  • Phase Configurations
    • Maximum (6-Phase + 2-Phase) or (5-Phase + 3-Phase)
    • Minimum (1-Phase + 1-Phase)
  • Driverless Configuration for Efficient High-Frequency Switching
  • Dynamic Output Voltage Transitions with Programmable Slew Rates via PMBus Interface
  • Frequency Selections with Closed-loop Frequency Control: 300 kHz to 1 MHz
  • Programmable Internal Loop Compensations
  • Configurable with Non-Volatile Memory (NVM) for Low External Component Counts
  • Individual Phase Current Calibrations and Reports
  • Dynamic Phase Shedding with Programmable Current Threshold for Optimizing Efficiency at Light and Heavy Loads
  • Fast Phase-Adding for Undershoot Reduction (USR)
  • Fully Compatible with TI NextFET™ Power Stage for High-Density Solutions
  • Accurate, Adjustable Voltage Positioning
  • Patented AutoBalance™ Phase Balancing
  • Selectable, 16-level Per-Phase Current Limit
  • PMBus™ System Interface for Telemetry of Voltage, Current, Power, Temperature, and Fault Conditions
  • Low Quiescent Current
  • 5 mm × 5 mm, 40-Pin, QFN PowerPad™ Package

Applications

  • ASIC Needs Dual Power Rails
  • High-Performance Processor Power
  • Networking Processor Power (Broadcom®, Cavium®)
  • High-Current FPGA Power (Intel®, Xilinx®)
  • High-Performance ARM Processor Power

Description

The TPS53681 is a multiphase step-down controller with dual channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET ™power stage. Advanced control features such as D-CAP+™ architecture with undershoot reduction (USR) provide fast transient response, low output capacitance, and high efficiency. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. The device supports fast dynamic voltage transitions with adjustable slew rate. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the systems. All programmable parameters can be configured by the PMBus interface and can be stored in NVM as the new default values to minimize the external component count.

The TPS53681 device is offered in a thermally enhanced 40-pin QFN packaged and is rated to operate from –40°C to 125°C.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
TPS53681QFN (40)5 mm × 5 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Application

TPS53681 fp_simp_app_slusct1.gif

Revision History

DATEREVISIONNOTES
June 2017*Initial release.