SLUSCD4A March 2017  – September 2017 TPS543C20

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5Electrical Characteristics
    6. 7.6Typical Characteristics
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
    4. 8.4Device Functional Modes
      1. 8.4.1 Soft-Start Operation
      2. 8.4.2 Input and VDD Undervoltage Lockout (UVLO) Protection
      3. 8.4.3 Power Good and Enable
      4. 8.4.4 Voltage Reference
      5. 8.4.5 Pre-Biased Output Start-up
      6. 8.4.6 Internal Ramp Generator
        1. 8.4.6.1Ramp Selections
      7. 8.4.7 Switching Frequency
      8. 8.4.8 Clock Sync Point Selection
      9. 8.4.9 Synchronization and Stackable Configuration
      10. 8.4.10Dual-Phase Stackable Configurations
        1. 8.4.10.1Configuration 1: Master Sync Out Clock-to-Slave
        2. 8.4.10.2Configuration 2: Master and Slave Sync to External System Clock
      11. 8.4.11Operation Mode
      12. 8.4.12API/BODY Brake
      13. 8.4.13Sense and Overcurrent Protection
        1. 8.4.13.1Low-Side MOSFET Overcurrent Protection
        2. 8.4.13.2High-Side MOSFET Overcurrent Protection
      14. 8.4.14Output Overvoltage and Undervoltage Protection
      15. 8.4.15Over-Temperature Protection
      16. 8.4.16RSP/RSN Remote Sense Function
      17. 8.4.17Current Sharing
      18. 8.4.18Loss of Synchronization
  9. Application and Implementation
    1. 9.1Application Information
    2. 9.2Typical Applications
      1. 9.2.1TPS543C20 Stand-alone Device
        1. 9.2.1.1Design Requirements
        2. 9.2.1.2Detailed Design Procedure
          1. 9.2.1.2.1Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2Switching Frequency Selection
          3. 9.2.1.2.3Inductor Selection
          4. 9.2.1.2.4Input Capacitor Selection
          5. 9.2.1.2.5Bootstrap Capacitor Selection
          6. 9.2.1.2.6BP Pin
          7. 9.2.1.2.7R-C Snubber and VIN Pin High-Frequency Bypass
          8. 9.2.1.2.8Output Capacitor Selection
            1. 9.2.1.2.8.1Response to a Load Transient
            2. 9.2.1.2.8.2Ramp Selection Design to Ensure Stability
        3. 9.2.1.3 Application Curves
    3. 9.3System Examples
      1. 9.3.1Two-Phase Stackable
      2. 9.3.2Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
    3. 11.3Package Size, Efficiency and Thermal Performance
  12. 12Device and Documentation Support
    1. 12.1Device Support
      1. 12.1.1Development Support
        1. 12.1.1.1Custom Design With WEBENCH® Tools
      2. 12.1.2Documentation Support
        1. 12.1.2.1Related Documentation
    2. 12.2Receiving Notification of Documentation Updates
    3. 12.3Community Resources
    4. 12.4Trademarks
    5. 12.5Electrostatic Discharge Caution
    6. 12.6Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Features

  • Internally-Compensated Advanced Current Mode Control 40-A POL
  • Input Voltage Range: 4 V to 16 V
  • Output Voltage Range: 0.6 V to 5.5 V
  • Integrated 3/0.9-mΩ Stacked NexFET™ Power Stage With Lossless Low-Side Current Sensing
  • Fixed Frequency - Synchronization to an External Clock and/or Sync Out
  • Pin Strapping Programmable Switching Frequency
    • 300 kHz to 2 MHz for Standalone
    • 300 kHz to 1 Mhz for Stackable
  • Stack 2X for up to 80 A With Current Share, Voltage Share, and CLK Sync
  • Pin Strapping Programmable Reference from 0.6 V to 1.1 V With 0.5% Accuracy
  • Differential Remote Sensing
  • Safe Start-Up into Pre-Biased Output
  • High-Accuracy Hiccup Current Limit
  • Asynchronous Pulse Injection (API) and Body Braking
  • 40-pin, 5-mm × 7-mm LQFN Package with 0.5-mm Pitch and Single Thermal Pad
  • Create a Custom Design Using the TPS543C20 With the WEBENCH® Power Designer

Applications

  • Wireless and Wired Communications Infrastructure equipment
  • Enterprise Servers, Switches, and Routers
  • Enterprise Storage, SSD
  • ASIC, SoC, FPGA, DSP Core, and I/O Rails

Description

The TPS543C20 employs an internally compensated emulated peak-current-mode control, with a clock synchronizable, fixed-frequency modulator for EMI-sensitive POL. The internal integrator and directly amplifying ramp tracking loop eliminate the need for external compensation over a wide range of frequencies thereby making the system design flexible, dense, and simple. Optional API and body braking help improve transient performance by significantly reducing undershoot and overshoot, respectively. Integrated NexFET™ MOSFETs with low-loss switching facilitate high efficiency and deliver up to 40 A in a 5-mm × 7-mm PowerStack™ package with a layout friendly thermal pad. Two TPS543C20 devices can be stacked together to provide up to 80-A point-of-load.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
TPS543C20 LQFN-CLIP (40)5.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

TPS543C20 schem2_page1_sluscd4.gif